Targeted Market Segments in Silicon Intellectual Property, IP, and EDA

Targeted Market Segments

DOLPHIN’s customers belong to six main segments:

Original Equipment Makers (OEM) for electronic systems,

Integrated Device Makers (IDM) for Integrated Circuits,

Fabless Suppliers of Integrated Circuits,

Silicon Foundries delivering silicon wafers or IC’s,

third-party Integrators for Systems-on-Chips (SoC) and

other Providers of Silicon Intellectual Property (SIP).

These segments are addressed with a two-pronged offering. On the one hand, SIP corresponds to the supply of Virtual Components (ViC) which provide reusable subsets for the hierarchical design of any SoC, an emerging market slightly above $ 1 Billion, but spread-out worldwide and ripe for internet-based growth. On the other hand, Electronic Design Automation (EDA), is around $ 3 Billion strong, but temporarily destabilized by the flight of major American talents to dot.com start-ups and stalled by the lingering doubt about its effectiveness at addressing the design productivity gap. So much so that, according to Gary Smith of Dataquest: "Five times more money is spent on internally-developed tools than on merchant tools". Typically, seven years after their founding of the Alliance for the Virtual Socket Interface, the big actors have not yet released a framework enabling a non-captive hierarchical design flow for SoC integration.

However the worldwide market of SIP block should represent $ 2 Billion in 2009, i.e. a compounded annual growth rate higher than 10 %. Such a growth rate thus is higher than that of the semiconductor market as a whole and particularly smoother in front of its cyclic phenomena.

To help clarify and standardize this concept of ViC (Virtual Component), DOLPHIN is an active member in that professional organization Virtual Socket Interface Alliance (VSIA). In fact, the misleading expression IP creates confusion since it may refer to know-how applied in custom design contract work, as well as to products prepackaged in "Design for Reuse" or "Design for Generations"! Since the legal issues of ViC Licensing are recent and evolving, DOLPHIN has actively negotiated Standard Terms with the best lawyers worldwide, so that the seemingly unattainable goal of a unique boilerplate is now attained. The ultimate test of the true product nature of any SIP pretense, with Off-the-Shelf guaranteed characteristics, is whether a quality control procedure is in place for ensuring that productization has been properly performed.

DOLPHIN’s two-pronged offering is based on complementary Product Lines with State-of-the-Art innovation for the Web:

FLIP™: catalog of Virtual Components as FabLess IP in Kits of Logic, Analog and Memories for SoCs demonstrating our KLAMS differentiation, with proprietary solutions enabling on-line generation and a set of FLexible Integration Platforms for SoCs, down to FPGAs for reaching-out numerous users,
MEDAL™: Virtual Platforms to facilitate SIP evaluation and design-in for SoC Integration comprise our Kits of Enabling Technologies, but also partake in the catalog of software components as "Missing EDA Links" up to enabling marketing and sales through B2B e.commerce, and even better: training and engineering support through Internet.

This dual offering subsumes, either for the analog side or for the hard level of circuitry, an Instantiation Development Platform based on a true language compiler GDS Compiler™ which enable the development of generators of analog or memory components and, on the logic side, cosimulation SUCCESS™ based on any Instruction Set Simulator (ISS) for any microprocessor centric SoC.

Typically the combination of development solution SUCCESS and either microcontroller architectures, Flip8051 on 8 bits and Flip80251 on 16 bits, constitute dynamic duos of SIP + EDA for Logic:

Systematically, the DOLPHIN focus is twofold:

on delivering "Virtual Application Schematics" and "Application Notes" for each ViC, where such schematics are said to be virtual since they explain the interconnections with real external discretes and with some ViC subset within a SoC, but also

on performing Virtual Yield Diagnosis, as a preview of fabrication issues.