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Differentiator

How to guarantee the successful integration of an Analog Front-End?

 

Integrating ever more functions into a SoC is a main trend both for economical and technical reasons:
Embedding functions is competitive for submicron process compared to PCBs which need multiple external ICs, as Audio DACs, Power Management Unit, etc. with multiple cost penalties, as interconnects, handling and inventory or scheduling.
On a technical point of view, embedding functions reduces volume, weight, power-consumption and critical interfaces at PCB level with related compliance issues, making the final SoC also more attractive for PCB designers.
Nonetheless this trend is opposed by some fears directly related to the integration savvy for analog functions. As THE Enabler of mixed-signal SoCs, Dolphin strives to eliminate all barriers to successful integration of a complete mixed-signal SoC.

 

 

Key Benefits

  • Offering best performances at system level compared to IC kits or System-in-Package solutions
  • Shortening the lag-time to Return on Investment through:
  • avoidance of unpredictable silicon re-spins through SoC-level Virtual Fab Process™
  • the capability to save silicon area by its optimal trade-off with performances
  • Maximizing the Return on Investment through:
  • High market differentiation thanks to flexible configuration of diversely embedded functions
integration circuit

 

Key Features

Diversity of experiences in SoC integration support is an irreplaceable source of know-how on priority issues which must be addressed through the Virtual Fab Process lest they would strike at silicon time! A wealth of ready-to-use templates, noise generators and EDA solutions ensues to grant the success of integration by check-up prior to commitment to silicon.

  • profiling the sensitivities of audio ADCs and audio DACs to jitter, power supply noises and drops, to disturbances from logic circuitry enables guaranteeing the same sound quality at SoC level as the embedded converter resolution.
  • achieving proper voltage regulation at SoC level and especially at the consumption points to avoid supply voltage bouncing - IR-Drops - with minimum penalty of silicon area.
  • Identifying profiling and modeling disturbance sources from logic circuitry - a Disturbance Generation Model - as well as their transmission channels - Disturbance Communication Channels - thanks to a real Rest-of-SoC Emulator.

 

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