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Presentation Sheet

shCODlp-100.01 - Stereo High Quality Audio CODEC

 

Amidst a rich à-la-carte offering, shCODlp-100.01 is an optimized and complete configuration around high performance DAC and ADC cores which provide a higher SNR for the lowest dynamic power.
Its small silicon area and low power consumption make shCODlp-100.01 THE high-end solution for upgrading portable audio applications.

 

schema

 

 

Applications

This CODEC is dedicated to high performance audio applications as diverse as:

  • Set-top box
  • PMP
  • DVB-H terminals
  • Portable HD-TV
  • Digital TV recorder
  • Wireless audio
schema

 

 

Benefits

  • Feature completeness:
    • ADC SNR of 95 dB and 100 dB for the DAC
    • 2 line-in and 1 microphone-in with AGC
    • 1 headphone driver and 1 line-output to drive external power amplifier
    • A mixer with “record while listening” function
  • Low power for performance : dynamic power as low as 7 mA in playback mode
  • Simplest Bill of Material :
    • Maximized yield with the best trade-off between silicon area and SoC / PCB costs
    • The headphone output application schematics is capacitor-less
    • The line-out application schematics is filter-less
  • PLL-less: single master clock generates all sampling frequencies.

 

 

Performances

  • 100 dB SNR per the “practical” benchmark for the DAC and 95 dB SNR for the ADC
  • Low current consumption 7 mA typ for analog and digital in playback mode
  • Typical output power at 3.3 V: 40 mW per channel on 16 Ω load for the headphone driver
  • Typical line-out signal level: 1 Vrms
  • Sampling frequency up to 96 kHz
  • Single frequency data flow synchronization: 12 and 16.9344 MHz
  • 3.3 V analog power supply
  • Compatible with any pure logic CMOS process (no MiM needed) at 0.13 µm and below

 

 

Features

  • Two stereo line-inputs and one microphone input
  • One capacitor-less headphone driver and one line-output
  • A mixer for the 3 input channels and DAC channel
  • Serial and parallel audio interface: 8-bit µC interface for control with I2C bridge.
  • 24 / 20 / 18 / 16 bit programmable word length
  • Selectable digital high pass filter for offset cancellation on ADC path

 

 

Typical PMP application

schema

 

 

Options for customized configurations "à la carte"

  • Digital sound enhancement options: Source™, Stream™, Cascade™
  • Various analog peripherals and logic options are available around the ADC and DAC cores to match customers configuration (on request)

 

 

Delivered under NDA

  • Preliminary front-end for design-in and reference application schematics
  • Product specifications and Price

 

 

Deliverables -hard-level for safest integration into any SoC

  • Specifications & User’s manual (incl. SoC integration guidelines)
  • Functional Digital Simulation Model
  • Industrial test specification
  • SCAN test patterns
  • Footprint (LEF) and Timing file for STA
  • LVS Sockets
  • PAD selection and reference layout
  • Layout (GDSII) and Flatten SPICE netlist for LVS purpose

 

 

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