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Flip80250-Typhoon - hard-eVSvHD 180GP
The hard Core for Power Savings!
Download Product Primer 
PRELIMINARY- Features and performances are subject to modification
The Flip80250-Typhoon is the Virtual Component at hard level for the most popular core of the i8051 legacy, as extended by the i80251. It is the 16-bit extension of the µP part awaited for, best for moving upwards compatibly from previous applications, at no risk for Time-To-Fab!
The architecture has been optimized for best Speed/Surface ratio, and Flip80250-Typhoon is proven optimal in TSMC 0.18 µm GP process for Low Power-consumption, thanks to the Voltage Scaling capability of the eVSvHD stem of SESAME.
Key features of 16-bit
- Most stingy in dynamic consumption
- Option for Lowest Noise emission
- Increase of processing speed an average of 2.0 times compared with i80C251
- Complete development Tooling:
- Exclusive cosimulator for mixed signal application
- Patented Smart-Clone
- Conservative pin assignment
- Large portfolio of peripherals at soft level:
- HDLC, SPI, I2C…
- SESAME library for optimizing
- On request:
- Optimization for any fab process
- Alternate optimizations (Noise…)
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Product overview
Starting for the Intel8051 legacy, the core 8050 has been freed from limitation of past technologies and augmented Compatibility as a 16-bit architecture.
The availability of Keil’s development software is a dual guarantee: of upward compatibility and of immediate availability for hardware-software co-verification.
Various flavors of optimization may be offered while using appropriate cell libraries and optimizing the logic synthesis and place & route steps. It results in product flavors optimized for either low power, high speed, low leakage, low noise, high density…
The value of such hard product is higher, the value of your SoC is higher too!
Configuration: I/O PIN location & routing constraints
Performances in typical case conditions (1.8 V-25°C) for TSMC 0.18 μm GP
Silicon Area |
Maximum Frequency |
Dynamic Power Consumption * |
Power Consumption in Idle mode ** |
Dhrystone Benchmark |
Static Power Consumption** |
0.42 mm2 |
200 MHz |
48 µA/MHz |
0.34 µA |
0.3 DMIPS/MHz |
0.34 µA |
* Average value when executing the Dhrystone benchmark
** The power consumption in idle mode is similar to the static power consumption because the Flip80250 is a processor (no peripherals included
Deliverables
SESAME library
- Verilog models, .lib, LEF, CDL, GDSII
Virtual Component
- Specifications & User’s Guide
- Functional Simulation models compiled on major simulators
- Firm Netlist
- Timing view for P&R (.lib)
- Abstract file (LEF)
- Transistor netlist (CDL)
- Layout (GDSII)
- Virtual Testbench
Software solutions and emulation (options)
- C-Compiler, Linker, Assembler, Instruction Set Simulator
- Smart-clone for hardware emulation and probing
- Rlink BIRD for embedded emulation and probing
Peripherals (options)
- Timers, UART, Watchdog, SPI, I2C, JTAG emulation…
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Cosimulator SUCCESS™
Mixed Signal Emulation serves to provide the software developer with a wide probing capability so as to trace-back a sequence of logic events or signal variations before a breakpoint. Separate ISS (Instruction Set Simulators) for simulating software, and electronic simulators like SMASH for simulating circuits, are readily available from diverse suppliers
HW & SW cosimulation
Debug Station
A complete set of Hardware emulator ranges from a mainly software solution (virtual emulator) as the most economic choice, through XSmart, the richest in Tracing features, up to BIRD, Built-in Real-time debugger. The optimal solution for each major goal!
Debug station Overview
< 16-bit overview |
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