Flip8050 Cyclone-eLLvHD - The hard Core for Low Power-Leakage!
Download Product Primer 
The Flip8050-Cyclone-eLLvHD is the Virtual Component at hard level (GDSII) for the most popular core of the i8051 legacy. Its pipeline architecture provides a processing speed-up of nine times on average when running at the same clock frequency as a standard i8051.
Flip8050-Cyclone-eLLvHD is proven optimal for Low Power-Leakage in the TSMC 0.18 µm GP fabrication process.
Flip8050-Cyclone-hard-uHDvLC-180GP is proven optimal for Low dynamic Power Consumption in the TSMC 0.18 µm GP fabrication process.
Key features of 8-bit microcontroller
- Lowest in power leakage
- Low dynamic consumption
- 9 times faster than the Legacy i80C51
- Dramatic reduction on execution cycle time
- Interface with synchronous memories
- Power Saving Modes: Idle, Power Down &CPMU
- Complete development Tooling:
- Innovative co simulator for mixed signal application
- Conservative pin assignment
- Large portfolio of peripherals at soft level:
- Powerful memory address extensions (MEU)
- SESAME library for optimizing
- On request:
- Optimization for any fab process
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Product overview
Starting with the Intel 80C51 legacy, the core 8050-Cyclone increases the performance of any 80C51/52-based application or can run the same application at a lower clock frequency in order to save power.
The availability of Raisonance and Keil’s Application Development stations is a dual guarantee: upward compatibility and immediate availability for hardware-software coverification. Moreover, their ISS (Instruction Set Simulator) benefit from cosimulator SUCCESS with mixed signal Smash with easiest integration for the lowest ”in-SoC” cost.
A range of options are offered for various flavors of optimization using appropriate cell libraries and optimizing from synthesis to place & route. It results in product flavors optimal for either low power, high speed, low leakage, low noise, high density…
The higher the value of such hard level product, the higher the value of your SoC
Configuration: I/O PIN location & routing constraints
Performances in typical case conditions (1.8 V-25°C) for TSMC 0.18 μm GP
Silicon Area |
Maximum Frequency |
Dynamic Power Consumption * |
Power Consumption in Idle mode ** |
Dhrystone Benchmark |
Static Power Consumption** |
0.24 mm2 |
50 MHz |
21 µA/MHz |
< 0.1 µA |
0.074 DMIPS/MHz |
< 0.1 µA |
*Average value when executing the Dhrystone benchmark
** The power consumption in idle mode is similar to the static power consumption because the Flip8050 is a processor (no peripherals included)
Deliverables
Virtual Component
- Specifications & User’s Guide
- Simulation models
- Timing view for simulation (SDF or TLF)
- Timing view for P&R (.lib)
- Abstract file (LEF)
- Transistor netlist (CDL)
- Layout (GDSII)
- Associated Testbench
Software solutions and emulation (options)
- C-Compiler, Linker, Assembler, Instruction Set Simulator
- XSmart-ICE for hardware emulation
- Rlink OCE for On-Chip emulation
Peripherals (options)
- Timers, UART, Watchdog, SPI, I2C, JTAG emulation…
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Cosimulator SUCCESS™
Mixed Signal Emulation serves to provide the software developer with a wide probing capability so as to trace-back a sequence of logic events or signal variations before a breakpoint. Separate ISS (Instruction Set Simulators) for simulating software, and electronic simulators like SMASH for simulating circuits, are readily available from diverse suppliers
HW & SW cosimulation
Debug Station
A complete set of Hardware emulator ranges from a mainly software solution (virtual emulator) as the most economic choice, through XSmart, the richest in Tracing features, up to BIRD, Built-in Real-time debugger. The optimal solution for each major goal!
Debug Station Overview
< 8-bit overview
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