Flip 8050 Wind - Integrate a Turbo 8-bit µC in your SoC!
Download Product Primer 
The Virtual Component Flip8051 Wind is a Turbo option of the 80C51/52 microcontroller. It is 100 % binary code upward compatible with the legacy 80C51/52. Its pipeline architecture provides an increase of processing speed an average of three times, when running at the same clock frequency as a standard 80C51 real component, but optimized to be the lowest cost 8051!
Flip8051 Wind, as any other member of the Flip8051 family of microcontrollers, is fully configurable, which means it is delivered in the precise configuration meeting user's requirements together with its Virtual TestBench for ensuring a SoC right-on-first pass per the VSIA standard.
Moreover it benefits from SUCCESS for easiest integration for the lowest “on-SoC” cost!
Main characteristics and perfomances of 8-bit microcontroller
- Main Characteristics:
- Fully synthesizable static synchronous design
- No internal tri-states busses
- Reduced execution cycle time thanks to pipelined architecture
- Power Saving Modes: Idle & Power Down & CPMU
- Interface with a/synchronous memories
- Performances (Dhrystone MiPS v1.1)
- Flip 8051 Wind = 0.024 MIPS / MHz
- Flip 8051 Wind = 3.63 MIPS @ 150 MHz
- Legacy 80C51 = 0.12 MIPS @ 12 MHz
- Virtual Clock
- Flip 8051 Wind @ 150 MHz ≅ 8051 @ 450 MHz
- Performance increase / 80C51 (running at 12 MHz):
- Flip 8051 Wind@150 MHz ≅ 38 x 80C51@12 MHz
- Power optimization with Frequency Tuning
- Flip 8051 Wind @ 4 MHz ≅ 80C51 @ 12 MHz
- The clock frequency can be divided by 3-times while
- executing the program in the same duration.
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Configuration
- 2 or 3 Timers / Counters - UART - Watch Dog Timer
- Program and Data Memory Expansion Unit (4 Mb / 16 Mb)
- Program Wait States and Data Wait States for slow peripherals and low cost memories
- Clock/ Power Management Unit enabling program selection between Fast and slow clocks
- Protection for Access to Memories for SoC anti Piracy with respect to any emulator interface
Virtual Testbench
VT-Flip8051 is an universal testbench for checking the functionality of any 8051 virtual component at any representation level (RTL down to silicon).
Verification Testbench
Deliverables at Firm and Hard levels
Historically first accelerated from the Breeze option cycle compatible with the legacy i8051
Implemented with the eLLvHD stem of the SESAME standard cell library
Firm level netlist and Virtual Testbench in VERILOG HDL
Functional Simulation Model compiled on any major VERILOG simulator
SESAME eLLvHD stem with VERILOG simulation model
EDA files: .lb, LEF, CDL, GDSII
Cosimulator SUCCESS™
Mixed Signal Emulation serves to provide the software developer with a wide probing capability so as to trace-back a sequence of logic events or signal variations before a breakpoint. Separate ISS (Instruction Set Simulators) for simulating software, and electronic simulators like SMASH for simulating circuits, are readily available from diverse suppliers
HW & SW cosimulation
Debug Station
A complete set of Hardware emulator ranges from a mainly software solution (virtual emulator) as the most economic choice, through XSmart, the richest in Tracing features, up to BIRD, Built-in Real-time debugger. The optimal solution for each major goal!
Debug Station Overview
< 8-bit overview
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