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Rock Vision : From Flip8051 to Flip80251 and APS-32
16-bit architectures are known historically for their economic efficiency: they provided the fundamentals for the minicomputer revolution of the seventies, then for the PC revolution of the eighties. Virtual Components of Silicon IP for Systems-on-Chip have emerged and thrived on both 8-bit and 32-bit architectures, and somehow inadvertently skipped its most promising notch.
Dolphin provides the most efficient Software Development Platforms from the now celebrated FLIP8051 up the compatibility ladder. It comprises the vital capability of a complete Station PRIDE™, "Panoply for Retargeting under an Integrated Development Environment", for migrating complex Software Applications upwards: these ultimately require the large addressing capability of a 32-bit architecture, even beyond the optimum ratio of performance per area, especially for the data bases at advanced technological nodes.
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A family with PRIDE™ Debug Station
The DOLPHIN architectural emphasis stems from the awareness that the i8051 legacy includes limitations from the bussing and packaging technologies of the seventies, while the i80251 includes those of the nineties. Structural improvements were mandatory to enable an error-free configuration process associated with a matching Virtual TestBench. It was needed to empower a bare 8050, to augment it firstly up to the 80250, then up to the state-of-the-art APS-32 core, with a properly separated constellation of peripherals, easy to enrich, especially with mixed signal peripherals, e.g. for power management and MEMS control.
A new vision of Development Platforms is thus enabled:
It starts with pure software solutions for Hardware-Software coverification by co-simulator SUCCESS™ including the Instruction Set Simulator ISS and the electronic mixed signal simulator SMASH. A complete mixed signal System now can be dealt with.
It paves the way to a patented hardware emulation Panoply enabling real-time capabilities: the POC™ for Processor Open Clone on JTAG interfaces, and the Built-In-Real Time Debugger, BIRD™.
It culminates with procedures for facilitating the retargeting of Applications, either from an 8-bit development to a 16-bit processor, or from a 16-bit development to the APS-32.
Main Characteristics and Performances
Fully synthesizable, static synchronous design
No internal tri-states busses
Interface with asynchronous and synchronous memories
Flip8051 |
Flip80251 |
FlipAPS32 |
Full binary code compatibility with the legacy 80C51/80C52 |
Enriched C51 instruction set (source mode): 16-bit & 32-bit arithmetic and logic instructions |
16 and 32-bit long instructions for superior code density with no mode switch |
A pipelined architecture that enables to reduce the number of clock per instruction |
A 4-stage instruction pipeline that enables to execute most of the instruction in a single cycle |
Pipelined Harvard architecture with completion of out-of-order instructions (memory latency hiding) |
64 K byte linear addressing space
Extension up to 4 M byte with paging |
16 M byte linear addressing space |
4 G byte linear addressing space |
Wind: 0.017 DMIPS/MHz
Cyclone: 0.047 DMIPS/MHz |
Typhoon: 0.296 DMIPS/MHz |
APS32: 0.710 DMIPS/MHz |
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