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Smart Clone - Patented hardware for emulation!
The "In-circuit emulator" Smart Clone provides the application program developer with an off-SoC solution which saves silicon area and offers the richest set of probing features.
The Smart Clone is a traditional hardware emulator, but our patented “Emulation by core externalization” puts the embedded microprocessor in idle mode in the SoC during debug, which is replaced by a clone embedded in the Smartbox: the Processor Open Clone or POC™.
Smart Clone is available for Flip8051/251 processors.
Key Benefits
- Breakpoint Insertion and Tracing controls are embedded within Smart-Clone which can save silicon area up to 10,000 Gates + trace memory
The same emulator is re-usable with low NRE for multiple usages of the core:
with any ASSP/SoC embedding the same µP
In case of SoC upgrade:
- If peripherals functions of µP are upgraded, the same emulator can be used
- If the µP itself is upgraded, the same emulator can be used by reprogramming the FPGA embedded into Smart Clone
- The complexity of SoC has no impact on the emulator complexity.
Product description
- Interface:
- Link with host-computer: USB 2.0
- Link with application board: JTAG interface (HE10 connector).
- Memory space: Up to 512 K-word for Code memory.
- Emulation frequency is up to 10 MHz.
- Trace memory:
- 128K x 72 bit recorded in real-time.
- 3 modes to start trace recording: continuous, rolling, trigger
- Complex trace trigger (combination or sequence of 8 events)
- Unlimited code breakpoints and code triggers thanks to a specific memory management (breakpoint is managed as a flag associated to each address) .
- Code coverage: Up to 512 k counters. 16 or 32 bit counter per code address.
- Several modes of execution control thanks to breakpoints: single step, C-line to line, step into, step-over, step-out, go to address…
< Emulation Debug Overview
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