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positioning of RAMs
ram_architecture

Range of Off-the-Shelf products: from 0.6 µm to 90 nm and soon 65 nm

A panoply of patents

  • Bit-cell mastery for reducing power consumption of memory planes (divided by 4) while improving speed and reducing area (XAM)
  • Design optimization for minimizing leakage of RAMs, standard cells… (LLA)
  • Full-differential read amplifier for speed optimization
  • Supply-switching for the best trade-off between low-leakage and high density (LLS)

The architectures and multi-foundry retargeting
20-year experience in designing embedded memories to select the architecture for optimal performance and for whatever preferred target process for both SpRAM and DpRAM.

Complementary features

  • Byte-write mode
  • Clear or erase function

 

 

positioning of ROMs

 

ROM

Off-the-shelf products range: from 0.6 µm to 90 nm and soon 65 nm

Our several patents

  • Compact ROM Matrix (dROMet)
  • Device for reading a storage (DELPHINUS-LP)
  • Multi-bit ROM bit-cell (tROMet)
  • Dual-bit ROM bit-cell (1/2T sROMet)

The architectures and the number of programming levels
Benefit from our 20-year-old experience in designing embedded memories to select the optimal performance architecture and then you can choose the number of programming levels among our metal ROM offering:

  • sROMet: one simple programming layer
  • dROMet: two layers for programming
  • tROMet: three layers for programming