Increase the battery-life of your SoC by a factor of 2 to 10 with Dolphin’s patented Silicon IP library !
“Leakage power” has definitely become the major minimization criterion for applications operating during some micro seconds per hour and targeting a battery-life of more than a year.
Enabling leakage savings in the range of 1/1,000 over traditional designs, Dolphin’s RAMs and cells to a new standard, based on the breakthrough design innovation of patent “Thick’n Thin”, offer the best answer to the ZigBee market in terms of static power consumption.
In a pure logic and General Purpose 0.18 um CMOS process using generic transistors, the leakage of a RAM instance of 8kx8 is as low as 2 nA and the leakage of a 100k-gate logic bloc is as low as 0.3 nA.
Then, in a SoC which embeds Radio, Analog, RAM and Logic circuitry, and where static power consumption due to the RAM and logic circuitry ranges between 1/2 and 9/10 of the total for the SoC, battery-life of the SoC can be increased by a factor of 2 to 10 by replacing any Silicon IP by Dolphin’s library of memories and standard cells !
< Ragtime Vision
Printer-friendly version
