The quest for The “RAM Benchmark”

To demonstrate the kind of alternative benchmark that would be complete from our point of view and readily applicable by anyone, while straightforward, our best guess is provided below as a complete and rather reasonable set of answers.

A range of simple RAM Benchmarks

For process TT
Typical power supply (e.g. VDD=1.8 V for 0.18 µm process)
Output capacitance: Cdout= 0.5 pf

A- Dynamic power consumption

50 % / 30 % / 0 % of clock cycles are inactive
25 % / 45 % / 35 % are Write cycles
25 % / 25 % / 65 % are Read cycles
Half of the address bits are switching
Words have length of x bits in 100 % of cases.

The "Cold RAM Benchmark"
Ambient temperature (25°C)

The "Cool RAM Benchmark”
Temperature (37°C)

The ”Hot RAM Benchmark”
Temperature (25°C)

Read/Write cycles are concerned with:

a uniform distribution of the y x-bit words
frequency of bit-switching on the Data Out bus: 50 % of cases
frequency of bit-switching in the memory content for write operation: 50 % of cases
frequency of bit-switching on Address bus: 50 % of cases

Other parameters play a role for reducing the dynamic power-consumption:

Read Margin: it can be more or less reduced but at the expense of yield.

Data IN/ Data OUT Bus: does the figure for power consumption take the output bus capacitance into account?

Frequency: the more favorable case is when power consumption is computed at a frequency corresponding to the cycle time!

B- Dynamic NOP (No OPeration) power consumption

100 % of clock cycles are inactive, clock signal is active
50% of the address bit are switching, at each clock cycle,
50% of the data input bits are switching at each clock cycle,
other input signals are at a static level (VSS or VDD).
The memory is powered on.

C- Power consumption from Stand-by leakage

Neither data transfers nor clock signals are active, and the select signal is Off.
All input signals (including the clock signal) are static at level VSS or VDD.
The memory is powered on.
This standby leakage consumption comes from the leakage of transistors mostly and diodes.
It is computed on the VDD power supply by simulation:
Memory is deselected on one cycle, then Stand-by power consumption computation is performed after a delay of several hundred of nanosecond.
This figure truly reflects the memory operation, better than pure computation from mean-value of leakage on both n and p type transistors.

RAM Benchmark Some samples

Benchmark Cold

50% are active cycles: 25% WR, 25% RD, 50% NOOP
3 lowest address bits in incremental mode
50% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words
50% of the Data Output bus bits are always switching with Cdout = 0 pf

Benchmark Tepid

50% are active cycles: 25% WR, 25% RD, 50% NOOP
3 lowest address bits in incremental mode + only one bit toggle at each operation cycle (Gray code)
50% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words
50% of the Data Output bus bits are always switching with Cdout = 0 pf

Benchmark Cool

70% are active cycles: 45% WR, 25% RD, 30% NOOP
3 lowest address bits in incremental mode + only one bit toggle at each operation cycle (Gray code)
50% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words
50% of the Data Output bus bits are always switching with Cdout = 0 pf

Benchmark Hot

100% are active cycles: 20% WR, 80% RD, 0% NOOP
3 lowest address bits in incremental mode + only one bit toggle at each operation cycle (Gray code)
50% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words
50% of the Data Output bus bits are always switching with Cdout = 0 pf

Benchmark Pessimistic

100% are active cycles: 50% WR, 50% RD, 0% NOOP
50% of the address bit are switching
50% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words
50% of the Data Output bus bits are always switching with Cdout = 0.5 pf

Benchmark Boil

100% are active cycles: 50% WR, 50% RD, 0% NOOP
100% of the address bit are switching
50% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words
50% of the Data Output bus bits are always switching with Cdout = 0.5 pf

Benchmark Green

Vdd_in = 0, Vdd_co = standard voltage as per techno*
No variation of the inputs
Integration of the leakage current after waiting for the stabilization of the bits lines

Benchmark Violet

Vdd_in = Vdd_co = standard voltage as per techno*
Memory initialization for one cycle (CSN = 1)
Then no variations of the input signals (including clock)
Integration of the leakage current after waiting for the stabilization for the internal nodes and current

*for example, SpRAM-uLCeHD URANUS 90LP = 1.2V

RAM ROM Power Control