The quest for The “ROM Benchmark”

To demonstrate the kind of alternative benchmark that would be complete from our point of view and readily applicable by anyone, while straightforward, our best guess is provided below as a complete and rather reasonable set of answers.

A range of simple ROM Benchmarks

For process TT
Typical power supply (e.g. VDD=1.8 V for 0.18 µm process)
Output capacitance: Cdout= 0.5 pf

A- Dynamic power consumption

50 % / 70% / 100% are active Read cycles
Half of the address bits are switching
Words have length of x bits in 100 % of cases.

The "Cold ROM Benchmark"
Ambient temperature (25°C)

The "Cool ROM Benchmark”
Temperature (37°C)

The ”Hot ROM Benchmark”
Temperature (25°C)

Read cycles are concerned with:

a uniform distribution of the y x-bit words
frequency of bit-switching on the Data Out bus: 50 % of cases
frequency of bit-switching on Address bus: 50 % of cases

Other parameters play a role for reducing the dynamic power-consumption:

Read Margin: it can be more or less reduced but at the expense of yield.

Data IN/ Data OUT Bus: does the figure for power consumption take the output bus capacitance into account?

Frequency: the more favorable case is when power consumption is computed at a frequency corresponding to the cycle time!

B- Dynamic NOP (No OPeration) power consumption

100 % of clock cycles are inactive, clock signal is active
50% of the address bit are switching, at each clock cycle,
other input signals are at a static level (VSS or VDD).
The memory is powered on.

C- Power consumption from Stand-by leakage

Neither data transfers nor clock signals are active, and the select signal is Off.
All input signals (including the clock signal) are static at level VSS or VDD.
The memory is powered on.
This standby leakage consumption comes from the leakage of transistors mostly and diodes.
It is computed on the VDD power supply by simulation:
Memory is deselected on one cycle, then Stand-by power consumption computation is performed after a delay of several hundred of nanosecond.
This figure truly reflects the memory operation, better than pure computation from mean-value of leakage on both n and p type transistors.

ROM Benchmark Some samples

Benchmark Nock

Clock signal is inactive
50% of the address bit are switching, at each clock cycle
the chip select Not signal is at a static level VSS
other input signals are at a static level (VSS or VDD)
the memory is powered on

Benchmark Cold

50% are active Read cycles
address bit are increased one by one
25% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words

Benchmark Tepid

50% are active Read cycles
all low significant address bit are switching
25% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words

Benchmark Cool

70% are active Read cycles
all low significant address bit are switching
50% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words

Benchmark Hot

100% are active Read cycles
50% of the address bit are switching
25% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words

Benchmark Boil

100% are active Read cycles
100% of the address bit are switching
100% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words

Benchmark Violet

Memory initialization for one cycle
De-selection of the memory (CSN active)
All input signals (including clock signal) are static at level VSS or VDD
Integration of the leakage current after waiting for the stabilization of the bits lines

RAM ROM Power Control