A panel of Front-ends for an easy evaluation of our memories:

 

SEDUCTION* Front-end:

Our memories seduce through their key performances and functionalities introduced in a presentation sheet (PS)

CHARM* Front-end:

Enables to choose the right architecture depending on the application requirements. Datasheet, preliminary performances and benchmarks available. Online Front-end generator available for a selection of instances.

DESIGN-IN* Front-end:

Soc integrators are provided with VHDL/Verilog simulation models, .lib with timing & power consumption in typical case conditions @ nominal voltage + Benchmarks. Online Front-end generator available for all instances in the flexibility of the generator.

INTEGRATION* Front-end:

ViC Specification, .lib for 3 to 5 corners according to voltage range, .dB, .lef, LVS sockets + Benchmarks. Online Front-end generator available for all instances in the flexibility of the generator, including abstract file for the safest integration into the SoC.

Note: “Nested doll” principle for our Front-ends: each level of Front-ends (Integration being the most complete) includes the benefits of the previous level(s).