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RAM Products

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Product name
Performance
optimization
voltage
range
Availability*
DOWNLOAD
65 nm
SpRAM-uLCeLL URANUS
Low Power
Low Leakage
nominal
TSMC LP
-
90 nm

SpRAM-uLCeLL URANUS
Low Power
Low Leakage
nominal
TSMC LP
presentation sheet
-
nominal
TSMC GP
presentation sheet
0.13 μm
SpRAM-uLL NEPTUNE
Low Leakage
0.9 V
3.3 V
CSM
UMC
1.35 V
1.65 V
TSMC LP
SpRAM-uLCeLL URANUS
Low Power
Low Leakage
nominal
TSMC LP
nominal
TSMC G
-
-
0.18 μm
SpRAM-uLL NEPTUNE
Low Leakage
0.8 V
3.3 V
TSMC GP
-
-
SpRAM-eLCvHD PLUTON
Low Power
High Density
nominal
TSMC GP
SMIC
-
-
SpRAM-eLVvHD PLUTON
Low Voltage
High Density
Down to
1.0 V
TSMC GP
SMIC
Silterra
-
-
DpRAM
Low-voltage
Low-power
High-yield
Down to
1.0 V
TSMC
0.25 μm
SpRAM-LP-JUPITER-XAM
Low Power
High Density
Voltage Scaling
1.2 V
2.75 V
TSMC
-
SpRAM-LL-NEPTUNE-XAM
Low Leakage
Low Power
Voltage Scaling
1.4 V
2.75 V
TSMC
0.35 μm
SpRAM-ULP-PLUTON-XAM
Low Power
Voltage Scaling
1.2 V
3.6 V
Specific process
SpRAM-HSHD-MERCURY
Hight Density
High Speed
3.0 V
3.6 V
TSMC
-
SpRAM-HS-MERCURY
High Speed
Low Power
3.0 V
3.6 V
TSMC
-
DpRAM-HS-MERCURY
High Speed
Low Power
3.0 V
3.6 V
TSMC
-
 

* Availability: Migratable to any other foundry on request

Add-on
 Embedded BIST
 
Embedded BIST
 for Low Voltage or Voltage Scaling
 
Voltage Regulators of logic islets with low power
 

 

 

A panel of Front-ends for an easy evaluation of our memories:

SEDUCTION* Front-end:

our memories seduce through their key performances and functionalities introduced in a presentation sheet (PS)

 

CHARM* Front-end:

enables to choose the right architecture depending on the application requirements. Datasheet, preliminary performances and benchmarks available. Online Front-end generator available for a selection of instances.

 

DESIGN-IN* Front-end:

Soc integrators are provided with VHDL/Verilog simulation models, .lib with timing & power consumption in typical case conditions @ nominal voltage + Benchmarks. Online Front-end generator available for all instances in the flexibility of the generator.

 

INTEGRATION* Front-end:

ViC Specification, .lib for 3 to 5 corners according to voltage range, .dB, .lef, LVS sockets + Benchmarks. Online Front-end generator available for all instances in the flexibility of the generator, including abstract file for the safest integration into the SoC.

 

Note: “Nested doll” principle for our Front-ends: each level of Front-ends (Integration being the most complete) includes the benefits of the previous level(s).