The Odyssey of RAMs Launching successful RAM instances and generators requires experience for mastering design quality, and know-how for reaching top performance. A success story overlasting generations of RAM architectures requires design robustness for multi-fab targeting which translates into high yield.   News Corner   July 14, 2008 - A new era for Dolphin Integration's embedded memories July 14, 2008 - Air Semiconductor and Dolphin Integration enable next generation GPS solutions 10.11.2007 - Ultra Low Power, Low Leakage and High Density 65 nm ROMs and RAMs Ultra high density and ultra low leakage ROM at 65 nm RAM for 90 nm nodes with dual optimization: for ultra-low power and for extremely high density. EE Times: Semi News Dolphin Integration is part of European "NanoCMOS" project Increase the battery-life of your SoC by a factor of 2 to 10 with Dolphin’s patented Silicon IP library! Dolphin’s Read-Only Memory generator embeds the highest density on standard CMOS - More on Dolphin's tROMet WARNING: Power-consumption benchmarks are under worldwide review due to new user trends in search of a yardstick (feel free to ask for it at ragtime@dolphin-ip.com); power-consumption figures currently computed on-line are "pessimistic".     Key objectives Providing low-power RAMs with optimal yield Addressing RAM static power issues through innovative design methods Ensuring right-on-first-pass SoC integration Ensuring high design yield and reliability Retargeting smoothly towards various fab processes   The DOLPHIN’S Intelligence applied… As early as 1987, at a time when embedded memories were mainly developed “in-house” at Integrated Device Makers, our first RAM design came-out right-on-first-pass with a 2.0 µm process! Even more importantly, our first efforts have been concentrated on developing a reliable method for thorough but fast qualification of generators capable of instantiating safely thousands of configurations on silicon. Since then, our offering of embedded RAMs has been enriched so as to grant optimal trade-offs between low-power (both static and dynamic) and low voltage operation, most of them silicon proven and all with worldwide customer references. Our current striving is to minimize static power consumption while providing high density at no design yield expense, which translates into architectural innovations, proprietary or under patents. Robustness throughout multi-fab retargeting of our RAMs, due to wise design choices, leads to error-free SoC integration with customers’ trust and the benefits of high yield. Thanks to a proven process of virtual characterization, with state-of-the-art simulation, our RAMs embedding bit-cells of foundry pushed-rule may serve as thorough "process qualifiers" for compatibility acceptance between different technological foundries! RAM performances result from know-how diversity: Robust schematics avoiding dependency on process and usage conditions Proper assessment of Read Margin and bit-cell stability for no loss of yield Standard practice of virtual characterization across the range of voltages Low-power and low-voltage architectures Bit-cell mastery Innovative combination of schematics and layout techniques     Find the optimal performance trade-offs! zoom in Range of Off-the-Shelf products: from 0.6 µm to 90 nm and soon 65 nm A panoply of patents Bit-cell mastery for reducing power consumption of memory planes (divided by 4) while improving speed and reducing area (XAM) Design optimization for minimizing leakage of RAMs, standard cells… (LLA) Full-differential read amplifier for speed optimization Supply-switching for the best trade-off between low-leakage and high density (LLS) The architectures and multi-foundry retargeting 20-year experience in designing embedded memories to select the architecture for optimal performance and for whatever preferred target process for both SpRAM and DpRAM. Complementary features Byte-write mode Clear or erase function

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