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The Odyssey of ROMs

Launching successful ROM instances and generators requires experience for mastering design quality, and know-how for reaching top performances.
A success story overlasting generations of ROM architectures requires design robustness for multi-fab targeting which translates into high yield.

 

News Corner
 

September 1, 2008 - the AURIGA sROMet completes our 65 nm Library

July 14, 2008 - A new era for Dolphin Integration's embedded memories

July 14, 2008 - Air Semiconductor and Dolphin Integration enable next generation GPS solutions

WARNING: Power-consumption benchmarks are under worldwide review due to new user trends in search of a yardstick (feel free to ask for it at ragtime@dolphin-ip.com); power-consumption figures currently computed on-line are "pessimistic".

 

 

Key objectives

  • Providing low-power ROMs with minimal area expense
  • Addressing fabricability issues of ROMs of large capacity
  • Ensuring right-on-first-pass SoC integration
  • Ensuring high design yield and reliability
  • Retargeting smoothly towards various fab processes
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The DOLPHIN’S Intelligence applied…

As early as 1987, at a time when embedded memories were mainly developed “in-house” at Integrated Device Makers, our first ROM design came-out right-on-first-pass with a 2.0 µm process!
Even more importantly, our first efforts have been concentrated on developing a reliable method for thorough but fast qualification of generators capable of instantiating safely thousands of configurations on silicon.

Since then, our offering of embedded ROMs has been enriched so as to grant optimal trade-offs between latest programming and smallest area from minimal to large capacity (several Mbits), most of them silicon proven and all with worldwide customer references.
Furthermore the striving to minimize power consumption while enabling operation at low supply-voltages (e.g. 1.0 V at 0.18 µm) translates into architectural innovations, proprietary or even patented.
Robustness throughout multi-fab retargeting of our ROMs, due to wise design choices, leads to error-free SoC integration with customers’ trust and the benefits of high yield.

ROM performances result from a diversity of know-how:

  • Reliable schematics avoiding dependency on process and usage conditions
  • Proper assessment of Read Margin to ensure optimal yield
  • Low-power and low-voltage architectures
  • Bit-cell mastery
  • Innovative combination of schematics and layout techniques

 

 

Find the optimal performance trade-offs!

 

ROM

Off-the-shelf products range: from 0.6 µm to 90 nm and soon 65 nm

Our several patents

  • Compact ROM Matrix (dROMet)
  • Device for reading a storage (DELPHINUS-LP)
  • Multi-bit ROM bit-cell (tROMet)
  • Dual-bit ROM bit-cell (1/2T sROMet)

The architectures and the number of programming levels
Benefit from our 20-year-old experience in designing embedded memories to select the optimal performance architecture and then you can choose the number of programming levels among our metal ROM offering:

  • sROMet: one simple programming layer
  • dROMet: two layers for programming
  • tROMet: three layers for programming