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Voltage Regulators of logic islets with low power

 

 

Acquiring SESAME for reducing power consumption of a SoC is motivated in two distinct cases:

  • either wanting to provide a SoC with a single logic Block with is own voltage,
  • or wanting to provide the complete solution with its own Power Management Unit.

Among the numerous design techniques which have been and continue to be developed, partitioning the SoC into voltage islets is growing as the most efficient and promising one. It is made possible thanks to a new vision of standard cell libraries, associated with RAM and ROM memory compilers, together with their customizable voltage regulators. Optimized Silicon IP blocks with Voltage Regulators are required in both cases, with and without Voltage Islets.

These are provided as companions to SESAME libraries and RAGTIME memories.

dcdc Voltage Regulators

 

Key Benefits

  • Reduce the SoC power consumption with a ratio of up to 6 for logic parts
  • Increase the battery-life of all portable devices
  • Reduce the costs of cooling in IC packaging and power supply components
  • Smooth and successful integration: consistent power management for low voltage standard cell library and memories
  

Product description

A pair of Voltage Adaptation Regulators eLV-VAR and eVS-VAR enables Customization to the islets requirements with various output voltages, fixed or programmable.
eLV-VAR optimizes the silicon area for the best trade-off with power efficiency.
eVS-VAR enables dynamic voltage scaling thanks to a digital programming of output voltage.
The output voltage range is compatible with RagTime memories and SESAME standard cell libraries offering. The input voltage is the standard voltage of the technological process.

 

Power saving thanks to eLV-VAR or eVS-VAR

Instance of a pure logic block of standard cells
=> Divide the power in mW by a ratio of 5 to 6!

DCDC Voltage Regulators

 

Application for a 0.18 mm process

DCDC Voltage Regulators

 

Specifications

  • DC-DC Silicon Overhead: some %, depending on logic islet power consumption
  • Only one external capacitor per DC-DC
  • Scaling step for the output voltage: 100 mV
  • Output voltage range : From core voltage down to half of core voltage.
  • Input voltage: Process core voltage
  

Deliverables

  • ViC final specification
  • Footprint
  • Integration guidelines
  • F&TDM Model and Documentation
  • LVS Socket
  • Flatten SPICE netlist for LVS purpose
  • GDSII database