Sesame uHDvLC 180 / 160 / 152 nm
ultra High Density |
very Low power Consumption
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Cost reduction in mature technological processes requires that IP providers take divergent paths: high density with the main set of design rules is a must, but support also of shrinkable rules is required.
Our library SESAME uHDvLC is already known for its cost reduction capability in the standard processes 0.18 and 0.13 µm.
SoC designers can now benefit from the availability of SESAME uHDvLC also in shrunk processes such as 0.16 µm and 0.152 µm.
SESAME uHDvLC is particularly recommended for applications like multimedia players, USB controllers, RFID and GPS/PDA.
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Key benefits of SESAME uHDvLC
- High density: up to 10% smaller area compared to the best high density alternatives
- Low power: up to 50% less consuming
- reduce the costs of system cooling and power supply components
- battery-life increase
- heat dissipation improvement
- reduced congestion after P&R thanks to less power straps needed
- reduced IR drop for the same area
- Maintain high density on speed constrained designs thanks to the composition with our High Speed library stem
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Product Features
- Operation voltage: 1.8V +/- 10%
- Inductor-less regulators can be provided as add-ons to reduce the Bill of Material
- Free tutorial for “Try and Buy” evaluation
- High design yield and reliability thanks to a thorough Virtual Fab Process™
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Deliverables
- Datasheet (html)
- Specification (pdf)
- Simulation models including back annotation features (VHDL/Verilog Tetramax compatible)
- View for Synthesis including Timing Analysis Model and Power models (.LIB and .db)
- Flattened Netlist for LVS (CDL)
- Footprint (LEF), antenna LEF and process LEF
- Detailed Physical Block Description (GDSII)
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Add-ons
- Integrated Clock Gating Cells
- Isolation cells
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