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Presentation Sheet

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SESAME uVSvHS 180 TSMC

 

 

ultra Voltage Scaling
very High Speed

 

 

Reducing the overall power consumption of a SoC is a critical issue for SoC designers, especially for battery-powered applications.
SESAME uVSvHS, referring to its Voltage Scaling and very High Speed capability, is fruits of our long time low power expertise.

SESAME uVSvHS is the optimal solution for applications like Zigbee, RFID, Portable Multimedia or Medical.

download evaluation Kits: uHDvLC 013

Key benefits of SESAME uVSvHS

  • Benefit from our patent for low voltage operation
  • Ultra Low power:
    • divide the power consumption of your SoC by up to 6
    • multiply the battery-life
    • decrease heat and life-stress of the circuit thanks to the low power supply
  • High speed optimized to enable functionality at ultra low voltage operation

Product Features

  • Available in TSMC G and ULL process
  • Operation voltage:
    • from 0.9V to 2.0V in G process
    • from 1.2 V to 2.0 V in ULL process
  • Optimized voltage regulators can be provided as add-ons
  • Comes with: ICG cell in order to reduce the power consumption at the functional level
  • Level Shifters can be provided on request
  • Free “Try and Buy” evaluation tutorial

 

spider 180 nm eVSvHD

 

Deliverables

  • Datasheet (HTML)
  • Specification (pdf)
  • Simulation models (VHDL/Verilog Tetramax compatible)
  • View for Synthesis including Timing Analysis Model and Power models (.LIB and .db)
  • Flattened Netlist for LVS (CDL)
  • Footprint (LEF), antenna LEF and process LEF
  • Detailed Physical Block Description (GDSII)
  

Add-ons

  • Optimized voltage regulators
  • Isolation cells
  • Falling edge flip-flops
  • Delay cells

 

Why uVSvHS?

• ultra Voltage Scaling: On the contrary of most of the so called ”low voltage” libraries which are only basic libraries characterized at lower voltage, the architecture of SESAME uVSvHS has been specifically designed to enable ultra low voltage operation.
In low voltage operation, the rising and falling edges of signals become longer and Flip-Flops are very sensitive to this phenomenon. The risk is then to have non functional Flip-Flops. A solution is to increase the number of clock buffers, but this rises the power consumption.
The Dolphin solution: a patented D-flip-flop which is less sensitive to clock edges and guarantees the functionality at very low voltage, which is not achievable with standard schematics.

• very High Speed: each cell has been carefully chosen and designed in order to enable a high speed at low voltage.

 

Illustration at 0.18 µm

courbe

 

 

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