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Presentation Sheet

SRI-1.8-1.0 | Inductorless switching regulator

 

 

Low power and low leakage applications require flexible and efficient power conversion to adapt the islet voltage supply to the function mode and reduce the power consumption. It scales down the regulated 1.8V core voltage to 1V reducing the power consumption of the logic block by a factor of 4 to 6.
The combination of a high efficiency and a low quiescent current makes SR-1.8/1.0 the ideal integrated companion of logic blocks targeting low power SoCs.
Its innovative inductor-less architecture stands out on BOM reduction making it the ideal solution for highly integrated applications.

 

Key benefits

Optimum performances for low power and low leakage applications:

  • Enable independent control of islet power rail to optimize the power consumption of the SoC
  • High power conversion efficiency
  • Ultra low quiescent current
  • Only 0.02 μA current consumption in bypass mode
  • Same clock as the logic load
  • Configurable output driver, according to digital islet current consumption requirement

Low Bill-of-Material:

  • Patent pending on inductorless architecture: no external inductor, only one external ceramic capacitor required
  • Optimized in density for the best trade-off with the output current
  • Cost efficient solution compared to external Power Management Unit.
  • Shrinkable to 0.16 μm processes.
patent

Applications

  • Sensors
  • RF devices
  • Low Power Microcontrollers
  • Low power SoCs

 

Key Features

  • Capacitor based switching regulator SR-1. 8-1.0 with integrated flying capacitor requiring only one external tank capacitor on its output.
  • Provide 1V from the core 1.8V regulated voltage.
  • Bypass mode allowing to supply the digital islet directly with the regulated 1.8V core voltage.

soc

 

 

spider

Performance

  • Input voltage: 1.8 V +/-10%
  • Output voltage: 1 V +/- 10%
  • Switching frequency: selectable from 0 to 50MHz
  • Quiescent current (bypass mode): 0.02 µA
  • Typical Output Ripple: 5 mV
  • Junction temperature range from -40°C to +125°C
  • Configurable (before delivery) output driver for a load current in the 10 mA - 100mA range; for optimal silicon usage
  • Portable to any CMOS logic process with 4 (or more) metal mask layers

 

Typical Application

typical efficiency

Delivered under NDA

  • Recommended application schematics
  • Product datasheet
  • Price

Deliverables - hard-level for the safest integration into any SoC

  • Specifications & User’s manual (incl. SoC integration guidelines & production test guidelines)
  • Functional Digital Simulation Model
  • Footprint (LEF) and Timing file for STA
  • DRC / LVS Sockets
  • PAD selection and reference layout
  • Layout (GDSII) and Flatten SPICE netlist for LVS purpose

Add-ons

  • Power-on-reset

 

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