| SEDUCTION* Front-end: |
Presentation sheet
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| CHARM* Front-end: |
- Charm “Try and Buy” evaluation tutorial
- ViC Specification including the performances for one representative corner of the stem
- Library view for Synopsys incl. Capacity Load- with 1 WLM; with the corner defined above; .lib contains area, timing and power consumption for the mentioned corner
- Verilog-HDL/VHDL simulation models
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| DESIGN-IN* Front-end: |
CHARM front-end but with all the corners for the STEM
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| INTEGRATION* Front-end: |
- Integration “Try and Buy” evaluation tutorial
- DESIGN-IN evaluator
- Abstract file compatible - incl. obstructions blocks => lef file DRC clean
- Antenna file
- Header LEF file
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