Graphic Design Solutions

 

According to the Dolphin strategy to focus on the Missing EDA Links, and to make them compatible with any Framework, the GDS product line is comprized of two major products:

SoC GDS to provide System-on-Chip Integrators with capabilities for structured layout and advanced Verification
GDS Compiler to provide Developers of “Retargetable Array Generators” (embedded memories, image sensors, pressure sensors…) with the ultimate design reliability in Generator Development

Soc GDS stars three major options:

• the fast and interactive Viewer to facilitate Design Reviews
• the unique builder of “Virtual Sockets” for design-in and extrusion
• the patented Virtual Scanning Microscope.

GDS Compiler has two crucial benefits:

• it lower the threshold of productivity and design safety so that developing a generator is preferable whenever ten configurations must be instantiated
• it enables procedural layout for microstructures granting immediate optimization of critical devices for any case of Engineering Change Order (ECO)

 

> ViC Enmeshing for SoC Harmony

SoC Designers suffer from the lack of « plug’n play » deliverables as well as of guidelines to ensure the optimal operation for each Virtual Component (ViC) for their integration into SoCs. But there is no single test method for the ViC "in SoC”, since it depends on the SoC architecture itself. Here are some solutions for a harmonious SoC!

Key issues Seamless insertion and assembly of Sockets into SoCs ViCs into SoCs Hardware/ Software Co-design Reliable ViC insertion verification Virtual Test Physical Test

Harmony in SoC at the expense of Flexibility in ViC

• For seamless insertion and assembly of ViCs into SoCs
  • Application schematics are part of ViC deliverables; they enable selection of the kit and interconnect schemes most appropriate for the application. See examples overleaf.
  • Simulatable but not synthesizable models e.g. Functional & Timing Digital Models (FTDM) for logic, analog and mixed signal ViCs: SoC integrators benefit from a pin-compatible model for fast simulation enabling functional and timing pin-to-pin verification.
  • Configurability of the kits of peripherals: ViCs are designed as peripherals around a core to grant optimal flexibility for the SoC architecture and testability with best Return-on-Silicon!
  • Virtual Sockets for SoC Floorplanning: be they at Soft-level for power and timing budgets or at Hard-level for area budgets and routing checks.
  • Provisions for keeping SoC disturbance emissions below the ViC Injected Disturbance Rejection Threshold (IDRT) to preserve signal processing performances: SNR, THD, Jitter…
  • Consistent design requires soft-level and hard-level ViCs to match criteria applied to synthesizers, automatic routers, thanks to a truly flexible standard cell library like SESAME
• For Hardware-Software Codesign
  • SUCCESS™ is the first solution for true cosimulation of mixed signal SoC, enabling coverification of Hardware, comprised of the configuration of virtual peripherals simulated with the mixed signal simulator SMASH, and software, comprised of the Application program running on the Instruction Set Simulator (ISS) of the microcontroller.
• To facilitate ViC verification in-SoC
  • Virtual Test: Detectors embedded in ViC HDL-models to support SoC Designers and guidelines for a proper enmeshing of the ViCs together.
  • Physical Test: Scanbus or even BIST are available as part of Dolphin’s ViCs to ensure total reliance on ICs for sensitive applications like medical…

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