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# 4 - Complete top-down or bottom-up capability to accelerate mixed-signal circuit development

 

Two sided Tower of Levels Multi-level Equivalence Checking

To promote mixed-signal simulation and explain multi-level concerns, a representation as the “Tower of levels” is particularly effective with its two sides, analog and logic. Multi-level zooming and equivalence checking is a critical capability for designers to reduce their development time by increasing the simulation speed and relevance at once.

two sided tower of levels

 

Multi-level and multiliguism

At the bottom, the Electrical level enables modeling with transistors: it is the world of SPICE. The upper level is that of RTL (Register Transfer Level) synthesized to Gates, for the logic side, and functional macro-blocks for Virtual Components or sub-blocks, for the analog side.
Behavioral descriptions start above for high level models at SoC level in HDL-AMS or C-like languages. The highest level is architectural for system level descriptions.

Now there is a deeper reason for wanting a simulator to be mixed-signal and that is whenever a pure logic circuit deals with signals of the real world, mostly analog. To a large extent, HDL-AMS have been designed for modeling signals exchanged and not the communicating processors!

Effective top-down and bottom-up design processes clearly require crossing linguistic boundaries. But it is crucial to grasp that Logic design is an essentially top-down process benefiting from the power of automatic synthesis, while Analog design is an essentially bottom-up process amenable to the construction of “generators” of flexible macro-cells.

 

Mixed signal Virtual Testbenches

SMASH is a single engine simulator. For mixing analog and logic parts, using a single engine is far less cumbersome than pairing separate ones. However, for simulating over very different domains, it makes sense to use cosimulation for the best of each world. DOLPHIN opens SMASH to cosimulation through SUCCESS™ where an Instructions Set Simulator (ISS) is coupled.

A convenient model for a component seen as a “Black Box” can then be conceived, with proper separation of

  • the input data signals (analog if coming from the physical world, digital of coming from nearby IC’’s),
  • the control signals (digital) preferably written in C-code and compiled,
  • the output signals, both logic and analog.

The Black Box is a pin-accurate representation in pure digital HDL, whether the innards are implemented with logic or analog circuitry.

The Virtual Test Bench is then expressed in VHDL-AMS.

virtual test bench

For the simplest cases where such a mixed signal model is unavoidable
For more advanced applications in line with VSIA recommendations, see ADmir

 

To cosimulate or not to cosimulate

The tower of levels thus must be extended with multi-domain cosimulation in the only manner which does not hurt, as demonstrated by SUCCESS, DOLPHIN solution for this issue. As natural extensions of the seamless mixed signal engine, two cases of cosimulation are considered:

  • Analog coupling to further Analog enables interfacing with an HF/RF simulator. The tower is enlarged to a new simulation domain beyond time-series (HF/RF being in a harmonic transform domain).
  • Logic coupling to further Logic enables interfacing with an Instruction Set Simulator (ISS). SMASH provides the exclusive ability to simulate application programs with mixed signal peripherals.

With such a solution, the complete benefit for system development is attained.

simulation

 

SMASH enables mixed-signal cosimulation without a cosimulator!
No cumbersome “backplane” to introduce delays and distortions…

Example through a PLL

This simple PLL may be simulate at different level (all combination are possible). Upon the solution selected, results will be tradeoffs between accuracy and simulation speed.
Hereafter, several solutions are presented.

SPICE / Verilog
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  • It is a very accurate solution.
  • However, VCO simulation takes 80% of the simulation time

SPICE / Verilog / ABCD
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The VCO is described in ABCD (Analog Behavioral C-based Description extending SPICE)

  • The accuracy may decrease
  • Simulation time is reduced (by about two)

Since RC Low Pass filter is not consuming much simulation time, it is kept unchanged.

SPICE / VHDL

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The logic description is in VHDL.

  • Speed and accuracy are similar to those with SPICE/VERILOG.

VHDL-AMS / VHDL

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The complete PLL may be described in VHDL/VHDL-AMS.

  • It is the best compromise between speed and accuracy.

Some SMASH option corresponds to your specific need!

 
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