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# 5 - Virtual Test & Diagnostic up to Virtual Yield Assessment and reliability insurance |
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Virtual Testing consists in applying a Virtual TestBench upon a circuit by simulation.
Virtual Instrumentation performs the development of a
Virtual TestBench interpretatively. It serves to prepare Real Instrumentation.
Virtual Test Programming performs the same function in a compiled mode,
best with SUCCESS. It serves to perform Functional Test and to prepare
Industrial Testing.
Benefits
Thanks to a Virtual Test Methodology (VTM), test development
can be performed during product development and design debug. In traditional
design methodology the Test Sequence can be programmed only after the
design is completed, and the Test developer has hardly any influence
over improving the circuit design! Testability then is only an afterthought…
The benefit of the VTM is the codesign of the test program and the circuit
on a simulator. VTM means a shorter, lower-cost design cycle, and consequently
reduced time-to-market. The test engineer can contribute significantly
in the areas of analog design-for-test and pre-fab device debug.
Test programs are available for use before prototype wafers are out
of fab, allowing rapid debugging of both design and test programs and
early customer delivery of quality first samples. Thus, the development
time of the test programs as virtual tests frees up the capacity of
a tester costing 1,5 M$!
SMASH “The VT&D champion”
Virtual Diagnostics consist in localizing design
defects by simulation; it serves conversely to:
- introduce defects for asserting testability
and test coverage
- model
a real silicon defect to enable “doubt-lifting” for Real Diagnostics.
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Automating diagnosis of analog weaknesses and bugs
Simulating an electronic design with typical parameters and input signals does not ensure that fabrication yield be acceptable. Dispersions of Fab-process parameters and of test signals must be accounted for during design.
Even worst-case simulations miss the point, and Monte Carlo analysis amounts to a dump of intractable data. Now SMASH enables thorough diagnostic of circuit bugs causing yield losses and precise pinpointing Imbalance Sensitivities!
Description of the ease-of-use
Monte Carlo analysis is mandatory for predicting design yield, but its reputation is at best to be awfully slow, at worst to be intractable. What was needed, SMASH has patented it! It goes further than traditional Monte Carlo analysis and
- diagnoses yield losses and provides efficient solutions for identifying and then optimizing transistors, resistors or capacitors sensitive to random dispersions such as mismatch effects,
- allows designers to detect sensitive combinations of such devices by locating each sensitive device!
…In brief, it allows reproducing a specific (faulty) simulation run, then applying the dispersion which caused the fault, either to only one device at a time, or to all devices except one. The aim is to detect which transistors, resistors and capacitors are sensitive to matching, offset and random dispersion effects.
Last but not least, thanks to its patent pending SWIFT simulation mode, SMASH can deliver the results from a Monte-Carlo analysis two to three times faster than simulators using a conventional Spice algorithm.
Patented methodology!
Optimizer of resilience to sensitivities in analog designs
Problem position
Even when the layouts of MOS transistors, often required to be similar in analog circuits, are strictly identical, their electrical behaviors may differ because of fabrication process dispersions. Random dispersions related to transistor matching, capacitance uncertainty… systematically degrade the expected characteristics and yield of analog circuits.
For instance, the yield of a memory block depends on quite a few stochastic distributions, such as: input offset of a read amplifier, voltage margin, skew between internal control signals, etc.
For predicting properly the analog characteristics and yield of such circuits, it is necessary to take into account crucial random dispersions in the simulation process for selecting the optimal circuitry.
Difficulty of solution
The well-known Monte Carlo technique is useful for predicting the effects of random dispersions, but it is not satisfactory. For optimizing a circuit with respect to analog characteristics and yield, it is necessary to understand why a given draw would drive to bad performances.
The Monte Carlo technique, while adequate for the final validation and acceptance of a design, is not effective during the constructive phase of circuit optimization along the design process.
This phase is prepared with an analysis of sensitivities to random dispersions.
The Dolphin innovation
Thanks to a patented solution based on the implementation of the "Imbalance locate" algorithm, SMASH enables you to diagnostic design yield losses in a deterministic way. This algorithm is powerful enough for detecting "touchy" pairs of transistors sensitive to matching, offset and random dispersion effects.
But, even better, it shall help you detect any "touchy" combination of resistors and capacitors, whatever their location on the circuit!
To resume, it allows you to reproduce a specific (faulty) simulation run, then to apply the dispersion which caused the fault either to only one device at a time or to all devices except one. The aim is to allow you to detect which transistors, resistors and capacitors are sensitive to matching, offset and random dispersion effects.
And the winner is...
of course the mixed-signal Virtual Components of the FLIP catalog: JAZZ for PLL's,
Converters and CODEC as well as RagTime for Embedded Memories!
Circuit reliability insurance with Dynamic Electrical Rules Checking (dERC) and Dynamic Specification Rules Checking (dSRC)
The dynamic ERC analysis is used to perform Electrical Rule Checks (ERC) and Safe Operating Area (SOA) checks in order to control that circuit variables (currents, voltages, powers, threshold and saturation voltages, internal variables,...) stay inside a given interval or do not exceed predefined limits.Static analyses examine circuits without input data and which therefore do not change over time. Static analyses can provide power consumption estimations, check transistor ratios, detect short-circuits and isolated circuits, as well as check other specialized electrical rules.There are two basic types of static analyses:
- Rule checking which ensures that a circuit obeys design environment restrictions and is divided into geometric design rules, which are concerned with the physical placement of the layout, and electrical rules, which examine the interconnection of the layout.
- Verification which ensures that a circuit obeys designer restrictions so that the intended behavior agrees with the actual behavior.
SMASH extends the notion of static ERC to dynamic ERC allowing electrical integrity checks on a circuit, using a programmable set of rules, in order to dynamically check for rule violations.All devices have safe operating areas which designers must check during design and simulation to guarantee that certain electrical design rules are never violated in order to avoid problems such as:
- gate oxide breakdown
- excessive heating
- source or drain to bulk junction breakdown
- ...
Traditionally, designers verify their circuits iteratively using simulators and analyze the results graphically. This process relies heavily on the designer's assumptions regarding which critical nodes or parameters must be verified in order to check that none of the conditions which might cause problems have happened. Therefore, it is necessary to be able to automatically detect rule violations that have occurred during a simulation.These electrical design rule checks are an important aspect in obtaining design compliance with the specifications and guaranteeing safe operation. The aim is to catch mistakes early in the design process and the rules enforce a consistent design methodology.
Dynamic electrical rule checking will be the basis of analog & mixed-signal circuit debug. In particular, it will allow the simulation to be paused or aborted when a rule is violated in order for the designer to be able to analyze and debug the circuit.
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