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SMASH 5.6 Verilog-AMS joining VHDL and SPICE
As the market is moving to nanometer technologies, the critical issue of transient noise takes a new urgency due to the sensitivity of analog and mixed-signal circuits, and even pure logic circuits. This is of course the case for PLL or oscillator designs, but also for evaluating the impact of noise injected by logic onto analog circuits.
SMASH 5.6 eases the practice of transient noise analysis, while leveraging model specific noise equations such as TSMC specific equations.
Key enhancements
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STI stress equations for BSIM3/ BSIM4 family of models including both Berkeley and TSMC specific equations
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Enhanced DSP toolbox for periodic signal characterization with jitters measurements and histograms
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Streamlined transient noise analysis, taking into account custom equations and parameters for noise
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Batch-mode data-extraction on FFT results
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Verilog-AMS small signal analysis
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Analog operators in Verilog-AMS such as transition filters, slew integrators or circular integrators
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Enhancement of time control for Verilog timing checks and VHDL VITAL
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ViC Disturbances Rejection
The success of SoC Integration of a mixed-signal ViC is unpredictable when high resolution analog or high accuracy logic is involved. SoC integrators are forced to waste at least 2 or 3 test silicon cycles. This “fail & retry” methodology leads to severe losses in performance and in yield, not to speak of costs, both direct (mask and engineering) and indirect (time to market and profit margin). The pragmatic approach needed, mingling Top-Down and Bottom-Up processes, has been developed through the use of DGP models (Disturbance Generation and Propagation). With its mixed-signal multi-level and multi-language kernel, SMASH provides the efficient solution for assessing and measuring the resilience of mixed signal Virtual Components to whatever disturbances injected by the Rest-of-SoC.
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