Presentation Sheet SMASH All-in-One Analog, Logic & Mixed-Signal Multi-Level & Multi-Domain Simulation     Integrating Systems-on-Chip must not demand the remodeling of virtual components, when embedding them, for making them fit the limitations of a specific simulator. Furthermore, efficient SoC Integration requires allowing simultaneous bottom-up and top-down design while enabling the designer’s choice of the appropriate abstraction levels to enable complete multi-level simulation for full-chip verification of mixed SoC. SMASH promotes simulation as natural as analog & mixed-signal schematics entry, using a natively mixed-signal multi-language circuit description, be it HDL text or netlist! Key Benefits Natural “All-in-One” approach of analog, logic & mixed-signal multi language simulation (SPICE, Verilog HDL, Verilog-A, VHDL, VHDL-AMS, ABCD, SystemC, C…) No backplane, no distortions, no delays! Easy combination of standard design languages at any abstraction level (electrical, structural, synthesizable RTL, behavioral, or architectural levels) Straightforward cross-language model instantiation using common language statements (SPICE/X…) Optimization of speed vs. accuracy trade-offs using models of the appropriate abstraction levels Flexible support of SPICE flavors (Hspice, Pspice, Eldo…) for easy integration into Design Chains Top-notch support of VHDL-AMS for multi-domain modeling and simulation Description of the solution For most EDA solutions, analog, logic & mixed-signal simulation implies cosimulation, i.e. coupling of two simulators interfaced through a “backplane” with cumbersome assembly of netlists, or explicit declaration of interfaces between analog and logic, i.e. manual setup of the complete simulation with limitations on the top-level description level. As a result, mixed-signal simulation is experienced as a tedious process where the fallback is, at best, to full SPICE with excessive accuracy and simulation time, at worst, to no complete simulation. Leveraging an optimized multi-domain single-kernel engine, a seamlessly mixed-signal simulator like SMASH enables natural design language mixing in the circuit netlist while ensuring efficient simulation with no distortions or delays added to signals. Using standard design languages (SPICE, Verilog/VHDL, HDL-AMS, ABCD/SystemC/C…), designers can easily combine blocks or IP from any vendor at any abstraction level, down to electrical and up to architectural. An "All-in-One" simulator enables the ultimate ascertainment of Multi-level Equivalence in simulations, both top-down and bottom-up, inclusive of Silicon Qualification.     < SMASH Options

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