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SMASH OPTIONS
ASIC Options
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Seduction
STD
LOG
CORE
OVI
HDL
MECHA
MEMS
PCB
Heart of SMASH
All-in-One Mixed-signal kernel update
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Graphic interface (GUI)
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Batch interface (CLI)
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Graphic waveform viewer
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Unlimited circuit size
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5 operating point heuristics
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4 analog solvers
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Languages
SPICE
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Verilog-HDL structural
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Verilog-HDL behavioral
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Verilog-A / Verilog-AMS
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Verilog-FD
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Pending integration of harmonic balance analyse for HF/RF extensions
VHDL
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VHDL-AMS update
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VHDL-FD
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C / SystemC
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ABCD
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Features
ASIC models (BSIM3v3, BSIM4v2, BSIM4v3, EKV, ACM, MM9, VBIC, MEXTRAM...)
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Relax
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VHDL VITAL
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Verilog SDF
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Advanced Features
Dynamic ERC
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Hi-Z Nets Detection
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Transient noise
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Phase noise
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Imbalance Locate
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Sensitivity Locate
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Jitter simulation
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Graphic User Interface for Trading-off Accuracy and Rapidity
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HDL Code Coverage
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Integrated HDL Debugger
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Waveform expression editor new
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Seduction
STD
LOG
CORE
OVI
HDL
MECHA
MEMS
PCB
Libraries
Emblem-Mecha
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Optional
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Emblem-Drive
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Diadem
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Add-ons
Device Modeler: Trans
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Iterator: Shaker
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Analyses
Operating point
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Transient
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Small signal
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DC Transfer
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Noise
Presentation sheet
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FFT
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Monte Carlo
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 VHDL
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Sweep
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Laplace
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Harmonic Balance
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Pending
Constellation & Interfaces
Cadence Composer (COACH)
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Optional
for Unix
Optional
for Unix
Optional
for Unix
Optional
for Unix
Optional
for Unix
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for Unix
Optional
for Unix
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Silicon Canvas Laker AMS (SMASHNET)
Presentation sheet
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Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
COSMOS for cosimulation with Simulink system-level blocks
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for
Windows
Optional
for
Windows
Optional
for
Windows
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for
Windows
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for
Windows
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for
Windows
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for
Windows
Optional
for
Windows
SUCCESS for hard/soft coverification
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for
Windows
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for
Windows
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for
Windows
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for
Windows
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for
Windows
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for
Windows
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for
Windows
Optional
for
Windows
SoC HLE (SLED) for schematic edition
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MemsMaster for MEMS modeling and simulation
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Operating Systems
Sun Solaris 7
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Linux RHL 7 to RHEL3
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Windows XP/vista
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