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At 90 nanometers and below it is no longer possible to separate design from manufacturing and as integrated circuits become progressively more complex, with 500 Mbytes GDSII files now the rule rather than the exception, the individual components must become increasingly more reliable if the reliability of the whole is to be acceptable.
SoC GDS Contrast is aimed at designers involved in custom layout, standard cell and memory design. Coupling the speed and power of SoC GDS Integrator with our patent pending eMicroscope technology, SoC GDS Contrast links schematic, simulation and layout views of a design to provide the reference tool for topological signal verification. By superposing simulation results directly onto the layout, highlighting signal sets which have changed state within your time-window, SoC GDS Contrast enables numerous topological signal diagnostics and verifications:
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> Key Applications
- Identify areas susceptible to excessive heating due to high signal activity detected during simulation and resulting in post-fabrication failure or unreliability
- Rapidly locate electro migration, IR-drop and cross-talk trouble-spots which would otherwise remain undiscovered until after fabrication
- Correct simulation “blind spots” caused by unequal surface coverage
- Locate “lost” cells within a layout as a function of net name
- Effectively identify jitter on busses
- Verify clock and signal distribution
- Topological diagnostic from design to production
- Virtual scan in preparation for – or to completely avoid – time-consuming and costly physical scanning experiments
- Localize real defects found on silicon during qualification by reproducing the qualification environment and defect in simulation for close topological analysis
- dERC violation verification and severity evaluation
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Trace signals directly on the layout through layers of hierarchy even where signal name changes, then watch and verify state changes (low, unknown, hi-Z, high) during simulation cycles or within specified time-windows. |
> Virtual Scanning Screen Shots gallery
> Thin Signal and Electro Migration
Due to continuing miniaturization of VLSI circuits, interconnects are subject to increasingly high current densities. Under these conditions, electro migration can lead to the electrical failure of interconnects in relatively short times, accentuation aging effects and reducing the circuit lifetime to an unacceptable level.
Highlighting during the simulation identifies the signal as high throughput. Closer examination confirms that the geometric bottleneck is in fact likely to result in post-fabrication design failure. |
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> Tuning Simulations: Memory Read Cycle
Coupling schematic, simulation output and layout for a memory-read cycle in the example below effectively identifies areas of the design activated by the simulation and locates areas of signals and interest, highlighting signals as they change and enabling rapid location of areas of signal activity.
At 1900ns into the simulation the read cycle is initiated. Distribution of the input Signal is clearly visible.
From 1902.5 to 1903 ns, address decoding followed by memory read is underway. The activation of the decoding lines and cell position is clearly visible and may be visually verified.
Finally, at 1907 ns, data become available at the outputs at the bottom of the layout.
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