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SESAME
A reduced library for increased performances

SESAME first has benefited from the developments made by the CSEM (Swiss Electronic and Microtechnics Center) since 98 for the ultra-low-power demanding watch industry.
Proposed since 2004, SESAME takes advantage of our 20 years of expertise in the design of embedded memories while relying on our unique and stringent qualification process.

 


 

Download the brochure in .PDF

 

The “multiple stem library”

SESAME is a mid-size grouping of specialized and well-structured “stems”: all such library stems are ultimately optimized for one prime criterion, e.g. Low Power Consumption (LC), High Density (HD), Low Leakage (LL), while simultaneously offering a good performance on a second criterion.

 

Maximizing rol

 

But, what are the differentiators of SESAME?

The best performance on a prime optimization criterion: the Stem.
Traditional libraries, classified as “Complex Cell Set Libraries” (CCSL), are unstructured bundles of cells trying to satisfy at once several optimization criteria: speed, power, leakage, area…

Opposite to this approach, SESAME is classified as a “Reduced Cell Stem Library” (RCSL): each library stem of SESAME is fruit of a handcrafted work of art, cell by cell. Indeed, each cell is carefully optimized at both electrical and layout levels to provide the highest performance on the chosen optimization criterion of the stem.

 

 

 

 

 

 

SESAME stems used stand-alone

 

 

 

Figure 3: naming convention
Exemple SESAME uHDvLC

Optimizations
Criteria

HD
High Density
LL
Low Leakage
HV
High Voltage
VS
Voltage Scaling
HS
High Speed
LC
Low power Consumption

Graduation of the Performance

u
Ultra
e
Extremely
v
Very
g
Good
m
Medium
p
Poor
b
Bad

 

 


 

 

The highest performance for highly constrained designs: “composition of stems”. Users may be concerned with a design where a strong constraint must be respected (for instance speed) while the circuit must be optimized in density. Mixing appropriate stems for composing a single circuit: one for the optimization, one for each applicable constraint, leads to top performances in highly constrained designs.

 

example of ultimate optimization for density and speed

 

The best performance for a specific design: the “branches”.
Designers may be aware that some RTL design make strong use of devices or features (e.g. adders versus combinatorial) which normally do not noticeably affect the circuit routing statistics, but which may be prevalent.

The “branches” are groups of cells optimized for a specific design style. Acquiring additional ”branches” for the prevalent devices or features of such a design style enables to obtain the highest level of optimization from the library stem for each design.

 

Design for Yield
Our libraries respect all the DRC rules and most of the DFM rules. Each time the best compromise is chosen between area and fabrication yield in order to guarantee the best RoI. We use the DFM rules as much as possible when they have no negative impact on the intrinsic cell performances.

 

The Virtual Fab Process - VFP: a default less quality assessment.
Only an exhaustive and rigorous validation process can ensure the required level of quality. But, the reliability of a standard-cell library can only be checked if the number of cells is reasonable as the cost and time for check-out increase exponentially with the number of cells. Thanks to our Virtual Fab Process, we calibrate and validate exhaustively our libraries all along the design process to ensure the highest yield.
Acquiring SESAME is the insurance of benefiting from error-prone libraries of cells whatever the SoC complexity.

 

 

 

 

 

Traditional tape-out vs. Virtual Fab Process