If your challenge is to reduce your application’s power consumption and to reduce its cost, you need PowerVision™ a EDA solution for “Frugal Innovation”.
With the growth of IoT market and the need for SoC with ultra-low power consumption using advanced design techniques such as multiple-island partitioning or DVFS, the issue of verification and securing integration of analog or RF IPs with digital blocks in a single die, in full awareness of power supply noise impacts, is more and more prevalent.
PowerVision™ Verification Platform provides a complete EDA solution for sizing the power regulation network optimally for each mixed signal SoC
Avoiding waste of silicon area, power consumption, BoM costs, packaging costs…
Preventing late discovery of performance drops of sensitive loads: RF sensitivity, audio ADC/DAC SNR, PLL jitter…
Avoiding costly design loops due to late discovery of noise issues during sign-off verifications
Best PPA & Lowest BoM and packaging costs
How to deal with noise issues also called “hot spots”
Nowadays, when building a SoC, architects have to deal with a growing number of potential noise issues also called “hot spots”. These issues are mainly related to analog performance or functionality, these noise challenges at stake are:
- High-frequency noise during each steady state (power supply noise, jitter…)
- Low-frequency noise during mode transition generated by logic blocks (in rush current, IR Drop…)
- Intrinsic noise of voltage regulator (specifically switching regulators)
- Self-pollution by the supplied load in steady states…
To address these hot spots, two types of checks must be performed started from architectural stage and then all along the SoC design flow:
- Mode Transition Checks (MTC): to check transitions between power modes at any level (System, SoC, IP...) to avoid any loss of functionality or performance.
- Noise Propagation Checks (NPC): to check noise propagation during steady state on clocks, power supplies and voltage references. The sensitive Silicon IPs must be validated to check that the noise is low enough to ensure the final performance.
PowerVision™ simulation window
Specific checks (non standard) thanks to PowerVision™ Mode Transition Check (MTC) enables to simulate the power integrity of the power supply at the input of a power domain.
Compare our solution with traditional solution
Late stage verification implying Time-consuming iteration loop.
- Unnecessary area/BoM/power consumption waste
- Experience-based handcrafting
- Power supply noise checks arrive too late in the design flow
- Incomplete views: PSRR instead of Power Supply Noise Tolerance Template (PSNT2)
Leading-edge EDA solution – PowerVision™: master the Noise Resilience for a Right-on-First-Pass SoC, from the architectural design phase, and all along the design-in stages.
- Minimizing design time/area/BoM/power consumption by identifying unnecessary margins
- Early-stage Noise Propagation Checks and Mode Transition Checks
- Secure the targeted performances of analog features sensitive to power supply noise
Bundled software components:
- SLED for graphic assembly of SoC synopsis and application schematics with model parameterization
- SMASH for performance simulations
- PowerVision™ plug-in to automatize the calculation of the Figure of Merit of a SoC architecture, the assessment of the Index Quality in terms of noise resilience and ensure the proper pairing between blocks
- PowerVision™ plug-in to automatize the Mode Transition Checks and the Noise Propagation Checks from the architectural design phase, and all along the design-in stages.
Libraries of components (various views):
- Parameterizable components and models
- Components of Dolphin Integration’s ViC
Documentation and training for effective transfer of know-how
- User Guide
- Application Notes