SoC GDS Layout Processor
SoC GDS offers an intuitive user interface, providing advanced productivity enhancing functionalities, throughout the design creation and validation chains.
SoC GDS addresses a wide range of needs, from quick and easy layout viewing, to final insertions of cells before mask generation, via advanced hierarchical integration of blocks, including solutions for preserving confidentiality in case of verifications.
This framework independent Streamer focuses on standard exchange formats for bridging proprietary EDA Frameworks.
Through dedicated options, SoC GDS fits the needs of Virtual Component providers, SoC integrators and process/product engineers. It is also the ideal solution to complete quality procedures for acceptance of layout databases by chip finishing teams, mask shops or silicon foundries.
- Integrated hierarchy browser
- OpenAccess, GDSII and LEF
- Ultra-fast layout loading and display
- Multi-platform GUI and CLI
- Interoperable with frameworks
- Graphical and geometrical comparison
- Virtual Socket Builder for generation of black boxes enabling verification and integration
- Virtual Cut for layout extraction
- Batch processing mode for automated verification and integration
Options for a wide range of applications
SoC GDS Analyzer is the entry-level option providing optimized display capabilities including color and pattern configuration file compatibility with Cadence for drop-in replacement or complementing in design flows.
SoC GDS Babelizer extends the speed and power of SoC GDS Analyzer with advanced hierarchical navigation, input format support complemented with OpenAccess and LEF, as well as (VC)LEF generation. Verification of layouts is accelerated through hierarchical graphic comparison of cells and hierarchical display of annotated nets.
SoC GDS Binder enables socket creation and verification for system-level integration of blocks and ViCs (Virtual Components). Delivery of layouts is accelerated by creation of LVS sockets (black box), hierarchical geometrical comparison of cells and a powerful interpreted scripting language for repetitive processing. An innovative feature for Virtual Cut allows to extract just a part of a layout for verification while totally preserving confidentiality of the rest of the SoC.
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