# SMASH Application Notes

## What is an application note?

On this page, you will find the introduction to the available application notes which demonstrate some of the capabilities of the simulator. You are free to distribute (not to sell!) these application notes without any restriction, as long as you do not modify a single character in their contents.

**If you download an application note, it would be really nice to have your feedback... Is it useful? Is it detailed enough? How could it be improved according to you? etc...**

## Verilog-A Compact Model Coding Whitepaper

(source: Dolphin)

The Verilog-AMS hardware description language [1] includes extensions dedicated to compact modeling, but does not define a reserved subset for compact modeling. This lack of specification combined with some SPICE related specificities are both responsible for the speed and memory consumption differences measured between simulations of Verilog-A compact models in Verilog-A simulators and SPICE simulators. That is the reason why, after presenting these differences, this paper [2] presents recommendations for developers of Verilog-A compact models who want to optimize their models for SPICE-like simulators and to facilitate the integration of said models into different simulators.Download the pdf

Please send feedback on this whitepaper to the authors.

## DxDesigner as a Mixed-Language Schematic Capture for SMASH™

(source: Desert Microtechnology Associates, Inc.)

This application note demonstrates through an example how DxDesigner (which will be referred to as ViewDraw in this document) can be used as a schematic capture tool to generate netlists that are easily compatible with the suggested file format in SMASHTM. An example project directory called “Viewnet” will be used to illustrate the proposed design flow. This directory is available upon request on the SMASHTM website as a zip file and should be downloaded, unzipped and placed in the reader’s simulation directory before continuing if the reader wishes to run the example step by step.

## Complete Simulation of Single Chip Camera Design (“Light In - NTSC Out”)

(source: Desert Microtechnology Associates, Inc.)

With the increasing complexity of mixed-signal chip design and the increase in mask costs, the need to perform full-chip simulations has become a virtual necessity. The time required to perform full-chip simulations in SPICE simulators, and even in Verilog-A simulators, is oftentimes overwhelming and does not give the engineer feedback quick enough to make meaningful corrections and gain a better understanding of how the designed circuit functions in the system. The true mixed-signal simulation capability of SMASHTM allows full-chip simulations through the use of mixed-language simulation. This allows the designer to model each portion of the entire design with varying degrees of accuracy depending on the aspect of the design that is being simulated and the time required to get data back for analysis.

## SWIFT for accelerating time-domain electrical simulations

(source: Dolphin)

Circuit simulators provide accurate time domain current and voltage waveforms from a device level description of an integrated circuit. However, as the size of the circuits increases, the cost of such analyses becomes prohibitive. For small circuits, the simulation time is generally dominated by the time required to evaluate model device equations, such as Berkeley BSIM3v3 transistor model equations, but, as circuit size increases, an increasing fraction of time is spent solving the sparse matrix built during circuit elaboration and filled with the results of the model device equations.

This application note presents two methods for accelerating time-domain electrical by a factor of x2 and x3 simulations applied to SMASH™ at no accuracy losses:

- a non-solving sparse matrix circuit equation,
- a fast and accurate model evaluation technique.

## From Chip to System Design using SUCCESS co-verification

(source: Dolphin)

In this paper we present solutions for the modeling of systems, containing electronic devices, non-electronic components and software.

We highlight the advantage of using the SUCCESS™ co-verification environment for:

- finding the most adapted micro-controller for an application
- developing and checking-up the application software
- simulating the whole system, including electronic and mechanical components and its interaction between them thanks to the use of elementary electro-mechanical models supplied by Dolphin Integration

## A Simulink/SMASH co-simulation interface

(source: Dolphin)

This paper presents the co-simulation interface between Simulink and SMASH. This interface allows the integration of HDL blocks (VHDL or Verilog) in Simulink via co-simulation of these blocks with SMASH.

First, it explains the interests in such an interface and its principle. Secondly, it focuses on a full running example based on a simple spring-mass-damper system. This system illustrates the interface capabilities for simulating mechatronic systems.

## Surface Micromachined Capacitive Pressure Sensor

(source: Gerhard-Mercator-University GH Duisburg)

The purpose of this application note is to present a capacitive pressure sensor system. The physical pressure is detected by a circular pressure element whose upper plate is deflected if it is exposed to an external gas or fluid pressure. The deflection results in a change of capacitance Cs between upper and lower plate. The readout circuit compares Cs with a reference capacitance Cr which is not sensitive to pressure changes. It is based on the switched capacitor technique..

## Surface Micromachined Deformable Mirror Device

(source: Gerhard-Mercator-University GH Duisburg)

The purpose of this application note is to present the suitability of our approach by simulating the deflection of a deformable mirror device (DMD) together with its controlling circuit. The DMDs are de ectable mirrors which are arranged in a matrix on the chip. Depending on the voltage at its electrode, each DMD can be deflected separately. In this way, the resulting phase or amplitude modulation of incoming light can be used to create a pixel image on a screen. Various schemes have been proposed for DMDs. Here, a simple, quadratic, reflecting plate is used.

## Automatic gain control

(source: Dolphin)

The purpose of this application note is to present different modeling approaches with the SMASH simulator, illustrated with the choice of amplifier model within a simple application, namely the amplifier gain control. The application context is briefly reviewed and we then focus our attention on the modeling. In order to decode DTMF signals of small amplitude, the gain of the amplifier has to be controlled. The input signals (IN) of the circuit have to be decoded according to their frequency. The trouble is that their amplitudes (from -45dBm to -4dBm) are too small to be detected by the decoder. Indeed the chosen decoder can only detect signals of at least -32dBm, up to -4dBm. A logic command (CMD), resulting of the input signal treatment, is therefore necessary to have a gain of approximately 15dB (with a 2dB margin) for the small amplitude signals (from -45dBm to at least -32dBm), and a unity gain in other cases. The gain control is achieved by altering the feedback resistor of the operational amplifier as detailed in the circuit principle.

## Modeling of comparators

(source: Dolphin)

This paper presents an overview of comparator's descriptions and simulation results with SMASH. Triggers, which use hysteresis, will be introduced as a generalization of comparators. The purpose of this application note is to show different approaches for modeling such comparators and triggers: * "electrical" macro-modeling, * "functional" macro-modeling, * behavioral modeling, which does not only implement a generic facility (just like macro-model) but also provides a "natural mathematical description" in C code.

## Switched current techniques

(source: Imperial College - London)

Competition in the area of mixed analog and digital MOS ICs has been pushing analog designers towards using pure digital VLSI/ULSI processes for both the analog and digital parts of the IC. Generally, the analog part of a mixed-mode IC takes longer to design but occupies only a small percentage of the chip's area. This trend not only calls for new analog design techniques fully compatible with pure digital VLSI processes [1] but also it reveals limitations in the use of purely analog, purely digital, or circuit-level-only simulators as design tools. This is particularly the case with current-mode analog sampled-data circuits (or switched-current - SI circuits), renowned for being one of the toughest kind of circuits to simulate [2]. They demand robust convergence algorithms coupled with realistic and continuous MOS models that will give meaningful results with reasonable simulation time, especially when fine-tuning circuit-level building blocks. For the fast and effective simulation of complete systems, it is necessary to use higher-level true-behavioral descriptions, formulated in a standard, non-proprietary language such as C; also desirable is an interface for standard HDLs

In its electrical and structural levels, SMASH can handle analog components as differential equations and digital components as Boolean laws and event-driven. At a behavioral level, circuit blocks can be substituted by either their Laplace-transform block or by a C-code model, ensuring quick system-level simulations. The use of the mixed-mode multi-level simulation engine of the industry-proven SMASH simulator is illustrated with the switched-current (SI) technique. We show how the use of options, models and simulation hierarchy can affect the simulation of SI circuits and how SMASH can be used to obtain flexibility and speed in the design phase. The robust algorithms in SMASH, the availability of realistic MOS models and real-time graphics processing are shown to allow simulation and visualization of the toughest SI designs in any region of operation of MOS transistors. At circuit-level SMASH accounts for non-ideal device characteristics and at system-level it combines descriptions of SI cells to avoid excessive simulation time. SMASH can easily handle typical mixed-mode systems such as PLLs [3] or sigma-delta data converters (analog modulator and digital filtering).

The first part of this application note deals with an example of a saturated, regulated-cascode SI memory cell. In the second part we use SMASH to simulate a new class of SI circuits using the S2I technique, for transistors biased in the transition of weak to moderate regions. In a third part we discuss the simulation of SI circuits at higher level to demonstrate the potential speed-advantage of higher level modeling.

## The ACM model and equations for SMASH

(source: LINSE - Florianopolis, Brazil)

This report presents the detailed model equations and parameters for ACM, which is a new MOS transistor model derived by LINSE, Florianopolis, Brazil. The model is implemented in SMASH since release 3.5, as the 'level 10' model. This model is particularly well suited for low power applications.

The ACM model was developed by LINSE laboratory (Florianopolis, Brazil). The authors are: Oscar da Costa Gouveia Filho, Marcio Cherem Schneider, Ana Isabela Araujo Cunha and Carlos Galup Montoro.

The model was developed by LINSE using the TRANS add-on, which allows external models to be implemented in SMASH. The model was developed and validated using the charge based model template in TRANS and then ported to level 10 in the commercial version of SMASH. The equations and parameters are fully documented in the application note. To introduce the model, here are some reprints extracted from this documentation:

ACM is a physically based model for the MOS transistor suitable for analysis and design of integrated circuits. The static and dynamic characteristics of the MOSFET are accurately described by single-piece functions of the inversion charge densities at source and drain. A new compact physical approach for saturation is presented. Short geometry effects are included using results previously reported in the technical literature.... ACM equations (currents and charges) have infinite order of continuity for all regions of operation. It is also charge-conserving and has explicit equations for its 16 transcapacitances.

...

ACM model is useful not only to simulate circuits with high current density but also low voltage operated circuits because it accurately represents the moderate and weak inversion regions.

...

Here is a summary of the ACM features :

- single-piece expressions, with infinite continuity
- source-drain symmetry of the transistor
- charge-conserving equations
- physically based equations for the vertical field dependance of carrier mobility, carrier velocity saturation and saturation voltage
- geometric dependence of electrical parameters
- technology independent equations
- easily measurable parameters
- small number of parameters

## Plots and simulation examples with the ACM model for SMASH

(source: LINSE)

A nice document prepared by LINSE laboratory, presenting characteristic plots of the ACM model, and also simulation examples of basic analog structures and circuits, with plots of the results. Somewhat big to download (about 500k) but it's really worth it if you are interested in MOS transistor modelling...

## Characteristic curves of semiconductor devices

(source: Dolphin)

A semi-conductor device is partly described by its voltage-current characteristic. The purpose of this application note is to point out the SMASH simulator capabilities to obtain these data interactively. To illustrate our purpose, we present classical semi-conductor devices which are the bipolar and the MOS transistors.

## Simulation d'une PLL (4046)

(source: Dolphin)

**NB: this application note is only available in French**

Cette note d'application présente un modèle comportemental du composant 4046. L'ensemble des fichiers est fourni sous forme d'une archive Winzip (.zip). Un fichier PDF décrit le fonctionnement du modèle et les simulations associées. Les schémas et symboles pour PROTEL sont fournis. Si vous vous intéressez aux aspects technique de modélisation, ou tout simplement si vous voulez disposer d'un modèle de PLL/4046

## Simulation d'un timer (555/556)

(source: Dolphin)

**NB: this application note is only available in French**

Cette note d'application présente un modèle comportemental du composant 555. L'ensemble des fichiers est fourni sous forme d'une archive Winzip (.zip). Un fichier PDF décrit le fonctionnement du modèle, ainsi que différents montages typiques, et les simulations associées. Les schémas d'application et les symboles pour PROTEL sont fournis. Si vous vous intéressez aux aspects technique de modélisation, ou tout simplement si vous voulez disposer d'un modèle de timer..

## Simulation d'un switch contrôlé en tension

(source: Dolphin)

**NB: this application note is only available in French**

Cette note d'application présente un modèle comportemental de switch contrôlé en tension. La modélisation de la variation de la résistance du switch entre les états passant et bloqué y est décrite. L'ensemble des fichiers est fourni sous forme d'une archive Winzip (.zip). Un fichier PDF décrit le fonctionnement du modèle, ainsi que différents montages typiques, et les simulations associées. Les schémas d'application et les symboles pour PROTEL sont fournis. Si vous vous intéressez aux aspects technique de modélisation, ou tout simplement si vous voulez disposer d'un modèle de switch...

## Oscillateurs sinusoidaux

(source: ISTG-Departement 3i)

**NB: this application note is only available in French**

Cette note d'application illustre l'utilisation de SMASH pour l'enseignement de l'électronique. Elle est extraite du cours "Fonctions électroniques" dispensé à l'ISTG (Institut des Sciences et Techniques de Grenoble - Université Joseph Fourier). La partie reproduite ici traite des montages classiques pour oscillateurs sinusoidaux. En particulier, le montage pont de Wien traite dans ce cours est simulé avec SMASH. Vous pouvez contacter l'auteur à l'adresse email suivante: gheeraer@lepes.polycnrs-gre.fr

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