Design Automation Conference
San Francisco, California, USA. June 25-26, 2018
Meet Yannick PAILLARD, Director Of Business Development. He will attend:
- the IP trackel panel - session 6 - on Monday 25, at 01:30 PM. Come to the stand #2008 to benefit from new techniques on how to minimize IC power consumption with PPA optimized IPs
- the TSMC OIP Theater on Tuesday 26, at 04:45 PM. Come to the stand #1629 to learn about the breakthrough silicon IPs and deal cost-effectively with the complexity of more energy-efficient SoCs
Addressing the energy-efficiency challenges of IoT end points
Every market research firm is forecasting that we will soon be surrounded by billions of IoT devices. If not all devices will connect to the Internet directly, as we do with our mobile phone, an increasing number of devices will have this capability. But unlike our phone, a single battery charge will need to last up to 10 years.
The design trade-off to achieve this low-power target is multidimensional, not to mention the constraint for having a small form factor and a competitive cost structure. At the heart of these IoT edge devices is an Energy-Efficient SoC, integrating RF signal processing, power regulation, network communication, AI computing together with some memory storage.