Need for A standard subset of Verilog-A for Compact ModelingMOS-AK 2009,at IHP in Frankfurt /OderG.Depeyrot, F.Poullet
April 03, 2009
Need for A standard subset of Verilog-A for Compact Modeling
MOS-AK 2009, 2-3 April 2009 at IHP in Frankfurt /Oder
Gilles DEPEYROT & Frédéric POULLET
Without any doubt, Verilog-A is now a standard language for compact modeling. But, much like for synthesis, a standardization of a subset of Verilog-A, along with a definition of good coding practices, is now needed to write efficient models that can be use directly by final users. This presentation will compare Verilog-A simulations with SPICE simulations of models generated using ADMS XML. In both cases, the same Verilog-A models are used, but contrarily to the simulator, ADMS XML only considers a subset of the Verilog-A language dedicated to compact modeling. For the final user, the main difference is not only the speed and the memory consumption, but also the integration of the model in a simulator with parameters and functionality shared by the different available models. We will focus on two functionalities available in SMASH: the simulation of noise in the transient domain, and SWIFT mode that speeds-up transient simulations by locally linearizing the model.
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