Spinner System by Dolphin Integration: optimized design and integration methodology based on pulsed latch for drastic area reduction in logic designsL.Jure
February 01, 2013
Spinner System by Dolphin Integration: optimized design and integration methodology based on pulsed latch for drastic area reduction in logic designs
Systems-on-a-chip (SoC) design complexity is continuously increasing over the years, and 100 Million gates circuits are now taping out. Additionally, the logic gate count has evolved so as to represent in average 50% of total SoC area. This rapid increase in the circuit complexity and the necessity to reduce costs, have resulted in a need for ultra high-density standard cell libraries.
For the majority of Silicon IPs providers, the area reduction of standard cell libraries, whatever is the technological process, is centered on the reduction of the number of tracks: speed critical designs rely on 12-tracks libraries, general purpose circuits leverage on 9-10-tracks libraries, while density optimized circuits are generally implemented with 6-7-tracks libraries.
Another path to improve the density of logic parts of the SoCs is to focus on the optimization of sequential cells, as 40% of logic area is generally made of sequential cells.
Like this, a new generation of standard cell libraries addresses the need for ultra high-density logic design through the use of low track cells, combined with pulsed latch cells, as the densest alternative to flip-flops.
As only less than 10% of designs are implemented with pulsed latches, it is essential to understand the principle and the art of using pulsed latch cells to reach the best density, together with the smoothest integration.
This article introduces the best technique for designing and implementing pulsed latch cells. You will know more about the major differences between pulsed latches and flip-flops. The article also presents the spinner system as developed by Dolphin Integration including optimized pulsed latch combined with pulse generator and methodology for seamless integration within standard implementation flow, which you can rely on to achieve unexpected density results. The last part of the article will be focused on practical examples proving the benefits of the spinner system for improving the density of designs at 65 nm.
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