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Verification of Mixed Signal System Design accelerated by a new Diagnostic Tool-Kit
ASIM 20. Symposium Simulationstechnik Cottbus, Germany
D.Dammers, F.Tissafi Drissi, M.Giroud, D.Schollän, L. M.Voßkämper

September 24, 2009


Time-to-market is still required to decrease in state-of-the-art design processes. Reli- able verification of complete mixed-signal systems, i.e. logic and mixed signal electronics and systems with their attached peripherals, such as sensors and actuators, is needed to be performed quickly to fit in the enhanced design process. While the verification of the logic part, mostly implemented in Verilog and VHDL, has gained a speed increase through the use of Accellera’s Property Specification Language (PSL), the analog part suffers from not being supported by this language. To speed up the verification of the analog part (SPICE, Verilog-A(MS), VHDL-AMS), innovation is needed. Based on the PSL principle, this paper presents an innovative solution for reliable and efficient valida- tion of mixed-signal circuit design which commonly makes use of multiple languages for modeling. As demonstrator, the electrical validation of an embedded memory design is used as starting-point.

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