Setup/hold interdependence in the pulsed latch (Spinner cell)

June 27, 2014

Introduction

The frequency of the very large Systems-on-Chip continuously increases over the years. Operating frequencies of up to 1 GHz are common in modern deep sub-micrometer application specific integrated circuits. The verification of timing in VLSI circuits is achieved by means of static timing analysis (STA) tools which rely on data described in the cell libraries to analyze the circuit. The characterization of the individual cells in cell libraries is therefore highly critical in terms of accuracy of the STA results. Inaccurate characterization of constraint timings causes the STA results to be either overly optimistic or pessimistic. Both cases should be avoided as the optimistic case can cause a fabricated circuit to fail, whereas the pessimistic case unnecessarily degrades circuit performances.

This article describes the setup/hold pairing for the standard cells and proposes a new method to characterize it accurately. The first part discusses the setup/hold constraints and the existing solution to model the setup/hold interdependence. The second part emphasizes on the Dolphin Integration solution to determine the setup/hold interdependence and the last part applies the new solution on the pulsed latch (spinner system).

To consult this article, please contact : libraries@dolphin-ip.com

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