A versatile Control Network of power domains in a low power SoC
G. Reveret

February 29, 2016

With the development of more and more power-consuming mobile applications, the battery lifetime has become the biggest challenge of a low-power System-on-Chip (SoC).
Success in designing a low-power SoC requires successive attention to five intertwined networks:

  • the exchange network between functional blocks through data busses,
  • the clock distribution network, possibly enabling clock gating and frequency scaling,
  • the voltage regulation network, possibly enabling Dual Voltage and Frequency Stepping (DVFS),
  • the control network of power islands, managing changes of power modes implying transitions of clock frequencies and voltage regulator states,
  • the application network which spans over the PCB.

Developing and verifying a control network in a low-power SoC is a challenging task, especially managing the different states of regulators and modes of power domains.
This article first describes state-of-the-art approaches to addressing this issue, and then delves into the solution promoted by Dolphin Integration to go further, thanks to the easy and secure Maestro™ solution to manage SoC power mode transitions.

To go further on this topic, discover the unique Maestro™ network.

 

Download this publication