FOUNDATION IPs: Standard Cell Libraries, Memory compilers, Power gating solutions

A broad offering of Foundation physical IP for low power applications

With its long lasting experience in designing best-in-class semiconductor IPs, Dolphin Integration provides embedded memory and logic library products for designers seeking low power with no trade-off on silicon area.

Dolphin Integration delivers a broad and consistent range of memory compilers and standard cell libraries, thoroughly validated with our Virtual Fab Process (VFP) stringent validation flow to ensure easy integration and high fabrication yield covering process nodes from 180 nm down to 22 nm.

Foundation IPs provided by Dolphin Integration provide embedded power management features (multi-Vt/multi-channel libraries, multi-VDD characterization, integrated power-gating, source-biasing...) that enable designers to explore trade-offs among performance, area, and power to generate optimal configurations that meet the specific challenges of each SoC subsystem.

More specifically, a dedicated offering for Always-On power-domains has been developed to achieve the ultra-low-power requirements in sleep modes of battery operated devices.

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Discover our solutions

Standard Cell libraries

  • Main logic libraries
  • Always-on libraries

Memory compilers

  • SRAM (Single and Dual Port)
  • Register Files (Single and Two Port)
  • Via ROM (metal ROM)

Power gating solutions

  • SESAME Island Construction Kit
  • CLICK

"Dolphin Integration enriches our ecosystem with low power and high density Foundation IP. This award recognizes their capability to provide a consistent offering of low-power IP in our specific process variants to address the low power consumption requirements of our customers."

Suk LEE, Senior Director of Design Infrastructure Marketing Division - TSMC

"Dolphin Integration regularly enriches our ecosystem with a large range of specialty and mainstream IP. […] This distinction [TSMC’s 2014 Award for the Open Innovation Platform’s Partner of the Year in the category of Specialty IP components] recognizes their capability to provide high quality IP in our specific process variants."

Suk LEE, Senior Director of Design Infrastructure Marketing Division - TSMC

"Dolphin team's prompt response to varies questions we came up with. Without the close cooperation between our two companies, we would not have finished the design with a newly developed library in such short time. In terms of support, Dolphin is one of the best in my experience."

Yongyao Cai, Director of Technology Partnership and Development - MEMSIC

Added value of our Memories and Logic libraries

Dolphin Integration provides solutions to meet the demand for low power by providing Foundation IPs supporting a broad range of operating modes and implementing (or enabling) a number of power management techniques in order to hunt down the micro-amps.

Moreover, Dolphin Integration continuously provides new features and methodologies to secure IP integration and to reduce the time-to-market.

Low Power

  • Expertise in Multi-Voltage-Supply (Multi-VDD) design
    • Low voltage, Dual rail memory (SRAM)
    • Low power Standard cell libraries operating near-threshold
  • Low power cache controller architecture, drastically improving latency and dynamic power of Flash memory accesses.
  • Multiple Power Management Modes for sRAM and ROM: stand-by, retention (with or without source biasing), shut down (with or without embedded switches)
  • Multi-Vt/Multi-channel length standard cell architecture
  • Power gating with state retention adding a Power Island Construction kit to our Standard cell libraries and completing the solution with our embedded TRC.

Easy Integration

  • Full EDA-flow support thanks to dedicated scripts facilitating the implementation of innovative solutions
  • A simple, safe and automatic IR-drop management during power-up of a power-domain thanks to the advanced power-gating solution
  • Foundation IP electrically, physically and EDA-view aligned with voltage regulators

Silicon Area Reduction

  • High density architecture for memories: up to 25% gain in silicon area
  • Ultra-high-density standard cell libraries with 6-Track or 7-track architectures
  • Patented spinner cell: up to 2x denser than conventional flip-flop

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