Embedded memory IP: Single-Port SRAMs

SpRAM CALYPSO

Single Port SRAM compiler - TSMC 28 nm HPM - Memory optimized for low power and high density - compiler range up to 640 k

Benefits

    • Configuration
    • HD pushed rule bit cell from foundry
    • Several transistor VT available
    • Innovative banking approach to propose several performance trade-offs for any memory size
    • Multiple form factors
    • Variable write-mask capability
    • Reach the highest density
    • Thanks to smart periphery design
    • Extend battery life
    • Partitioned array to reach ultra low power consumption
    • Stand by mode
    • Data retention mode at nominal voltage (0.9 V +/-10%)
    • Minimum data retention voltage at 0.6 V +/-10%
    • Make safe the integration
    • Data range flexibility allows easy addition of bits for ECC purposes
    • Address range flexibility allows easy addition of single rows
    • Robust power grid sizing to prevent IR drop and electromigration effects
    • Metal 4 partially available for routing
    • Column and line redundancy feature available

Performances

Variantes
VT Bit cell
VT Periphery
Operating Voltage
Capacity
Option mode
28 HPM
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