Catalog of Microcontroller cores
Product:riscy-D1

riscy is RISC-V compliant core IP targeting high processing power and energy efficient battery powered System On Chip

 

RISC-V is a state-of-the-art and open source Instruction Set Architecture (ISA). It benefits from a fast-growing and dynamical software ecosystem to enable the new generations of System On Chip (SoC).
The RISC-V riscy is a high computing power and ultra-low power processor core implementation for new generations of SoCs such as Wearables, IoT devices, sensors...
riscy implementation supports privileged modes execution and can be extended by several add-ons: FPU, DSP and Bit Manipulation.

Key Benefits of riscy-D1

  • Low silicon costs
    • small gate count: 40 kGates
    • high code density with compressed ISA
  • Ultra low power: less than 10 μW/MHz (TSMC 40nm LP)
  • Best-in class computing power: 3.6 CoreMark/MHz
  • Fast Time to market
    • Configurable subsystem enabling faster SoCdesign
    • AMBA AHB-Lite and APB compatible interfaces
    • Early software prototyping with SmartVision IDE
    • Wide RISC-V software ecosystem
  • Fully compliant with RISC-V ISA - RV32 IMC and F option
    • Compressed Instruction Set (C option)
    • Multiplier and divider (M Option)
    • 32 general purpose 32-bit registers
    • Optional Flotaing Point Unit
  • Custom processing addons
    • DSP extension
    • Bit manipulation instructions
  • Privileged execution modes supported
  • Optional 1/3/32 cycles multiplier
  • Up to 32 interrupt sources with 2 cycles latency in addition to the current executed instruction

 

 

Block Diagram


Get access to the complete product primer of riscy-D1

 

Key Features and Performances

  • Architecture: 4-stage pipeline
  • Computing power:
    • 3.2 Coremark / MHz * Coremark/MHz
  • Address space: 4 Gbytes
  • ALU: 32-bit
  • Peripheral bus: APB 32-bits
Performances per process node*
40nm
Power Consumption (µA/DMIPS)
<10 *with IC compila
Area (mm2)

*Evaluation conditions
Use of the high density and power optimized Sesame libraries from Dolphin Integration
Configuration: CPU + 1 timer + I/O ports
SS, Vdd-10%, 125°C, 50 MHz
post-synthesis (no P&R) with clock gating, no scan insertion

Peripherals

To suit all user requirements, the set of peripherals delivered with riscy-D1 is entirely configurable.
Among its peripheral offering, Dolphin Integration can provide R-Stratus, a cache controller enabling speed improvement and power consumption minimization when using Non Volatile Memories (eFlash, EEPROM...)

Applications

Internet of Things, Wearables, Touchscreen, Smart Card, Audio Processing, Medical, RFID, Image Processing

Development tools

SmartVision, Innovative IDE for application software development and debug

BIRD Falcon on-chip debugger for hardware debug

  • Scalable embedded debug solution enabling to achieve the optimal trade-off between debugging features and silicon cost
  • Debug software embedded in SmartVision
  • S-Link USB adapter
    • 2-wire TWIG interface
    • 4-wire JTAG interface
    • cost effective
    • high debug performances


smartVision
Overview of SmartVision interface

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Deliverables

  • Verilog or VHDL netlist
  • Source code (optional)
  • Testbench with documentation for checking the functionality of any configuration of the Flip80251 Hurricane at any representation level (RTL down to silicon).

Robustness is ensured

For more than 15 years, Dolphin Integration has built a testsuite for checking the functionality of any configuration of the riscy-D1 at any representation level (RTL down to silicon).The testbenches have evolved a lot thanks to users feedback.
The testbench is delivered with its documentation to our microcontroller core users so that they can apply it on their own project and ensure functionality.

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