Catalog of Microcontroller cores

zeroriscy is RISC-V compliant core IP targeting low silicon area and energy efficient battery powered System On Chip


RISC-V is a state-of-the-art and open source Instruction Set Architecture (ISA). It benefits from a fast-growing and dynamical software ecosystem to enable the new generations of System On Chip (SoC).
The RISC-V zeroriscy is an ultra-dense and ultra-low power processor core implementation for new generations of SoCs such as Wearables, low-cost MCUs for consumer and industrial devices.
zeroriscy implementation is the perfect trade-off for minimal silicon impact and consequent energy efficiency and computing power.

Key Benefits of zeroriscy-D1

  • Ultra low silicon costs
    • small gate count: 16 kGates
    • high code density with compressed ISA
  • Ultra low power: less than 4.4 μW/MHz (55 nm TSMC uLP eFlash)
  • High computing power: 2.6 CoreMark/MHz
  • Fast Time to market
    • Configurable subsystem enabling faster SoCdesign
    • AMBA AHB-Lite and APB compatible interfaces
    • Early software prototyping with SmartVision IDE
    • Wide RISC-V software ecosystem
  • Fully compliant with RISC-V ISA - RV32 IMC
    • Compressed Instruction Set (C option)
    • Multiplier and divider (M Option)
    • 32 general purpose 32-bit registers
  • Optional 1/3/32 cycles multiplier
  • Up to 32 interrupt sources with 2 cycles latency in addition to the current executed instruction



Block Diagram

Get access to the complete product primer of zeroriscy-D1


Key Features and Performances

  • Architecture: 2-stage pipeline
  • Computing power:
    • 2.6 Coremark / MHz * Coremark/MHz
  • Address space: 4 Gbytes
  • ALU: 32-bit
  • Peripheral bus: APB 32-bits
Performances per process node*
Power Consumption (µA/DMIPS)
4.4 *with IC compila
Area (mm2)

*Evaluation conditions
Use of the high density and power optimized Sesame libraries from Dolphin Integration
Configuration: CPU + 1 timer + I/O ports
SS, Vdd-10%, 125°C, 50 MHz
post-synthesis (no P&R) with clock gating, no scan insertion


To suit all user requirements, the set of peripherals delivered with zeroriscy-D1 is entirely configurable.
Among its peripheral offering, Dolphin Integration can provide R-Stratus, a cache controller enabling speed improvement and power consumption minimization when using Non Volatile Memories (eFlash, EEPROM...)


Internet of Things, LCD Controller, Touchscreen, Industrial, Audio Processing, Medical, RFID, Image Processing

Development tools

SmartVision, Innovative IDE for application software development and debug

BIRD Falcon on-chip debugger for hardware debug

  • Scalable embedded debug solution enabling to achieve the optimal trade-off between debugging features and silicon cost
  • Debug software embedded in SmartVision
  • S-Link USB adapter
    • 2-wire TWIG interface
    • 4-wire JTAG interface
    • cost effective
    • high debug performances

Overview of SmartVision interface

Related products

Libraries of Standard cells and memories

  • optimized for high density and low power consumption
  • enabling island partitioning

Power regulators to build an optimized SoC architecture for the lowest power consumption

High resolution analog converters for audio or measurement applications


  • Verilog or VHDL netlist
  • Source code (optional)
  • Testbench with documentation for checking the functionality of any configuration of the Flip80251 Hurricane at any representation level (RTL down to silicon).

Robustness is ensured

For more than 15 years, Dolphin Integration has built a testsuite for checking the functionality of any configuration of the zeroriscy-D1 at any representation level (RTL down to silicon).The testbenches have evolved a lot thanks to users feedback.
The testbench is delivered with its documentation to our microcontroller core users so that they can apply it on their own project and ensure functionality.

  • Receive our catalog