SoC FABRIC IPs for Energy Management

Under the spotlight at microelectronics symposiums this fall
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Get a head start

In a bid to lower power consumption in sleep and active modes, companies face increased complexity in SoC architectures and in their implementation.
Designers can now rely on breakthrough SoC Fabric IPs to safely manage energy management in any SoC, whatever its complexity: partitioned with power islands, supporting AVFS/DVFS or body biasing...

Meet us this fall in the USA or China to discover how adopting our complete solution of Fabric IPs can help designers enhance SoC PPA by up to 30%, save up to 4 months of TTM and reduce design risks significantly.

Learn more

Chip
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TSMC OIP Ecosystem Forum
USA, CA, Santa Clara, Sep. 13, 2017

Speech presentation: SoC Fabric IPs to enable DVFS

Live demonstration: WhisperTrigger, ultra-low power Voice Activity Detector IP

Video broadcasting: Outcome of Taishan demochip in TSMC 55 nm uLP eF, which rely on innovative SoC Fabric IPs, to succeed right-on-first-pass the design of an low-power SoC partitioned with power domain.

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SMIC Technology Symposium
China, Shanghai, Sep. 13, 2017

Live demonstration: WhisperTrigger, ultra-low power Voice Activity Detector IP

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IP-SoC Days
China, Shanghai, Sep. 14, 2017

Speech presentation: Improving Battery Powered Device Operation Time Thanks to Power Efficient Sleep Mode

Live demonstration: WhisperTrigger, ultra-low power Voice Activity Detector IP

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SMIC Technology Symposium
China, Beijing, Oct. 12, 2017

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Nanjing SOI Workshop and Tutorial
China, Nanjing, Sep. 21, 2017

Speech presentation - 4:30pm : Embedding power regulation & activity control networks for best SoC PPA
Registration

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The 5th Shanghai FD-SOI Forum
China, Shanghai, Sep. 26, 2017

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