Dolphin Integration offers the Veda benchmark to assist SoC Integrators in their permanent search for minimizing costs and maximizing the performances of each design.
With the Veda benchmark, it is now easy to estimate the area after P&R and the power consumption of your logic design - including RAM, ROM, Standard Cell Library - when embedding Dolphin’s Panoply to perform a benchmark against any other solution.
Key Benefits of the VEDA Benchmark
- Reliable estimation of the performances of a specific logic design
- Comparative evaluation of a Panoply of "memories + standard cell libraries"
- Easy estimation of the performances
- Assess the performances of your current panoply and compare with results for Dolphin’s Panoply
- Benchmark of silicon area, power consumption
- It takes around 30 minutes to get the comparison results
- Universal benchmark
- The Veda benchmark can be applied for any silicon IPs
- For standard cell libraries
Fill in the area values for each cell of your library. These values can be found in the .lib file and are prefilled-in for Dolphin’s library
Repeat the same steps for the other criterions: dynamic power, leakage
- For memories
Fill in the area values for each memory instance. These values can be found in the .lib file and are prefilled-in for Dolphin’s library
Repeat the same steps for the other criterions: dynamic power, leakage, speed
Specify the switching activity of each memory instance
- For the logic block
Specify the size of the logic block
Specify the clock rate
Specify the switching activity
- Get the results and compare the performances of 2 solutions at SoC level
The output is the overall expected performance of your specific SoC including area and power consumption.
- Receive our catalog