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Foundry Sponsored Libraries Catalog Logo foundry sponsored


 


 

 

Standard cell libraries

Always-on logic library
10 track thick oxide standard cell library at GF 55 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
SESAME BiV - 10 tracks
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GF 55 LPx, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the use of a patented flip flop.
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GlobalFoundries
55 LPx
55 Array
Main Logic Library
6 track Ultra High Density standard cell library at TSMC 55 nm
SESAME uHD - 6 tracks
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Foundry Sponsored, TSMC 55 LPeF, SESAME uHD (HVT) for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).
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TSMC
55 LP_eFlash
55 Array
9 track standard cell library at TSMC 55 nm
SESAME 9T - 9 tracks
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Foundry Sponsored, TSMC 55 uLP, Sesame 9T (eHVT), a unique architecture based on 9-track cells, optimized for High Density and Low Dynamic Power allowing users to create faster SoC than with 7-track libraries.
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TSMC
55 uLP
55 Array
6 track High Density standard cell library at TSMC 55 nm
SESAME HD - 6 tracks
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Foundry Sponsored, TSMC 55 uLP, SESAME HD DV (eHVT) provides the best trade-off between area and power achieved from an innovative cell design enabling 6-track cells and 1P3M SoC implementation.
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TSMC
55 uLP
55 Array
6 track Ultra High Density standard cell library at TSMC 130 nm
SESAME uHD - 6 tracks
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Foundry Sponsored, TSMC 130 BCD, SESAME uHD (SVT) for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).
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TSMC
130 BCD
130 Array
6 track High Density standard cell library at TSMC 180 nm
SESAME HD - 6 tracks
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Foundry Sponsored, TSMC 180 eLL, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-track cells and 1P3M SoC implementation.
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TSMC
180 eLL
180 Array
Power gating library
CLICK - The universal solution of power gating for the whole SoC
CLICK
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Global Foundries 22 nm FDX, CLICK, power gating cells to create a ring of switches in order to ease the integration of hard macro and provide automatic control of in-rush current during wake-up.
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GlobalFoundries
22 FDX
22 Array

Memories

1 Port Register Files
Single Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 40 k
1PRFile AURA DV
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Foundry sponsored - Single Port Register File compiler - TSMC 55 nm uLP - Memory optimized for high density and low power - Dual Voltage - compiler range up to 40 k
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TSMC
55 uLP
55 Array
Single Port Register File compiler - Memory optimized for high density - Dual Voltage - compiler range up to 40 k
1PRFile AURA DV
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Foundry sponsored - Single Port Register File compiler - TSMC 90 nm uLL - Memory optimized for high density - Dual Voltage - compiler range up to 40 k
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TSMC
90 uLL
90 Array
Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
1PRFile AURA
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Foundry sponsored - Single Port Register File compiler - TSMC 90 nm LPeF - Memory optimized for high density and high speed - compiler range up to 40 k
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TSMC
90 LP_eFlash
90 Array
Single Port Register File compiler - Memory optimized for ultra high density and high speed - compiler range up to 20 k
1PRFile AURA
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Foundry Sponsored - Single Port Register File compiler - TSMC 110 nm HV_1.5V_5V - Memory optimized for ultra high density and high speed - compiler range up to 20 k
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TSMC
110 HV_1.5V_5V
110 Array
2 Port Register Files
Two Port Register File compiler - Memory optimized fore high density and high speed - compiler range up to 320k
2PRFile ERA
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Foundry sponsored - Two Port Register File compiler - TSMC 55 nm HV - Memory optimized fore high density and high speed - compiler range up to 320k
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TSMC
55 HV
55 Array
Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
2PRFile ERA DV
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Foundry sponsored - Two Port Register File compiler - TSMC 55 nm uLP - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
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TSMC
55 uLP
55 Array
Two Port Register File compiler - Memory optimized for high density and low power optimized - compiler range up to 40k
2PRFile ERIS
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Foundry sponsored - Two Port Register File compiler - TSMC 90 nm LPeF - Memory optimized for high density and low power optimized - compiler range up to 40k
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TSMC
90 LP_eFlash
90 Array
Dual-Port SRAMs
Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
DpRAM ERA DV
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Foundry sponsored - Dual Port SRAM compiler - TSMC 55 nm uLP - Memory optimized for high density and low power - Dual Voltage - compiler range up to 256 k
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TSMC
55 uLP
55 Array
Dual Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 80k
DPRFile ERIS
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Foundry sponsored - Dual Port SRAM compiler - TSMC 90 nm LPeF - Memory optimized for high density and low power - compiler range up to 80k
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TSMC
90 LP_eFlash
90 Array
Single-Port SRAMs
Single Port SRAM compiler - Memory optimized for ultra high density and low power 3ML- compiler range up to 320k
SpRAM LYRA
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Foundry sponsored - Single Port SRAM compiler - TSMC 55 nm HV - Memory optimized for ultra high density and low power 3ML- compiler range up to 320k
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TSMC
55 HV
55 Array
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640k
SpRAM RHEA
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Foundry sponsored - Single Port SRAM compiler - TSMC 55 nm HV - Memory optimized for high density and Low power - compiler range up to 640k
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TSMC
55 HV
55 Array
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320k
SpRAM RHEA
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Foundry sponsored - Single Port SRAM compiler - TSMC 55 nm LP - Memory optimized for high density and Low power - compiler range up to 320k
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TSMC
55 LP
55 Array
Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
SpRAM RHEA DV
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Foundry sponsored - Dual port SRAM compiler - TSMC 55 nm uLP - Memory optimized for high density and low power - Dual Voltage - compiler range up to 256 k
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TSMC
55 uLP
55 Array
Single Port SRAM compiler - Memory optimized for ultra high density and high speed - Dual Voltage - compiler range up to 640 k
SpRAM RHEA DV
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Foundry Sponsored - Single Port SRAM compiler - TSMC 85 nm UP - Memory optimized for ultra high density and high speed - Dual Voltage - compiler range up to 640 k
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TSMC
85 UP
85 Array
Single Port SRAM compiler - Memory optimized for high density and low power - Dual voltage - compiler range up to 640 k
SpRAM RHEA
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Foundry sponsored - Single Port SRAM compiler - TSMC 90 nm LPeF - Memory optimized for high density and Low power - Dual voltage - compiler range up to 640 k
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TSMC
90 LP_eFlash
90 Array
Single Port SRAM compiler - Memory optimized for ultra low Leakage and high density - Dual Voltage - compiler range up to 640 k
SpRAM RHEA LL DV
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Foundry sponsored - Single Port SRAM compiler - TSMC 90 nm uLL - Memory optimized for ultra low leakage - Dual Voltage - compiler range up to 640 k
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TSMC
90 uLL
90 Array
Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler up to 64 k
SpRAM AURA
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Foundry Sponsored - Single Port SRAM compiler - TSMC 130 nm BCD - Memory optimized for ultra high density and high speed - compiler up to 64 k
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TSMC
130 BCD
130 Array
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 kb
SpRAM RHEA
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Foundry sponsored - Single Port SRAM compiler - TSMC 180 nm uLL_HV - Memory optimized for high density and Low power - compiler range up to 320 kb
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TSMC
180 uLL_HV
180 Array
Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
SpRAM PLUTON DV
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Foundry Sponsored - Single Port SRAM compiler - TSMC 180 nm eLL - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
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TSMC
180 eLL
180 Array
Via ROMs
sROMet compiler - Memory optimized for high density and high speed - compiler range up to 2M
sROMet TITAN
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Foundry sponsored - sROMet compiler - TSMC 55 nm HV - Non volatile memory optimized for high density and high speed - compiler range up to 2M
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TSMC
55 HV
55 Array
sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1 Mbits
sROMet TITAN DV
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Foundry sponsored - sROMet compiler - TSMC 55 nm uLP - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1 Mbits
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TSMC
55 uLP
55 Array
Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
sROMet PHOENIX
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Foundry Sponsored - Metal programmable ROM compiler - TSMC 90 nm LPeF - Non volatile memory optimized for low power - compiler range up to 1024 k
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TSMC
90 LP_eFlash
90 Array
Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 256 k
sROMet CASSIOPEIA
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Foundry Sponsored - Metal programmable ROM compiler - TSMC 130 nm BCD - Non volatile memory optimized for low power - compiler range up to 256 k
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TSMC
130 BCD
130 Array
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