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Added value of microcontroller IP cores offering


Memory sub-system area minimization

Reducing the silicon area of microcontroller sub-system requires minimizing the area of the microcontroller core plus its program memory (located in RAM).

The 80251/80351 instruction set architectures reduce the program memory area by improving code density. When associated with our Flip 80251/80351 implementations, the microcontroller cores area themselves are optimized.

The sub-system area savings reach up to 54% when comparing Flip80351 Zephyr versus Flip8051 Cyclone.

Area of microcontroller cores with associated program memory

Power consumption of Dolphin Integration’s microcontroller cores versus processing power*

Low power optimization

The power consumption of the microcontroller sub-system is optimized thanks to:

  • denser code reducing the number of memory access,
  • faster execution of instructions enabling the microcontroller core to be more often in power saving modes,
  • low power implementation with clock gating and enable signals on combinatory logic.

Power consumption is divided by 7 when comparing Flip80351 Zephyr versus Flip8051 Cyclone.

Application specific requirements

Microcontroller cores from Dolphin Integration offer a coprocessor interface.

This interface favors the association of a dedicated coprocessor with the microcontroller core to meet application specific requirements. Such an approach avoids using more complex general purpose microcontroller cores which will consume more and waste silicon area.

Key benefits of using coprocessors:

  • optimized and application-oriented instruction set
    • audio, cryptography, touchscreen...
  • specific data width to match data types used in application software
  • specifically addressable memory space
  • smart distribution of tasks enabling management of power modes
  • faster execution of the application software

*MAC: Multiplier and Accumulator / ALU: Arithmetic Logic Unit / ASU: Addressing and Sequencing Unit