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R-Stratus-LP - THE solution to significantly reduce power consumption of flash memories

Discover R-Stratus-LP

Microcontroller IP cores

8-bit, 16-bit and 32-bit microcontroller IP cores and embedded software development tool

We offer a wide range of microcontroller cores, starting with the 8-bit industry standard 8051, extended with 16-bit 80251 compatible, and going up to RISC-V 32-bit.

All our offering was built in order to insure a smooth evolution from CISC solutions to new generation of RISC microcontrollers 16 and 32-bit.

Various peripherals such as I/O ports, timers, co-processors, memory interface... are also available to fit specific application requirements.

Together with its microcontrollers cores, we provide the most efficient application software development solution: SmartVision™. SmartVision™ embeds advanced application software debug capabilities thanks to the modeling and simulation of the complete sub-system including processors, memories and peripherals. SmartVision™ also includes BIRD™ for on-chip debug.

We provide also a AHB/APB compliant Cache controller to meet a growing demand for both energy efficient and faster SoC with Non-Volatile Memories (NVM).

The microcontroller offering from Dolphin Integration enables SoC designers to drastically reduce their Time-To-Market with the most optimized solution for their application requirements.

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"We selected the MCU core from Dolphin Integration for its reliability. Dolphin Integration's MCU core has already demonstrated its maturity, as it was used in ASICs designed to replace standard components after their have become obsolete."

Ryan Xu, CTO - Beijing TMC

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i51 compatible ISA – RISC-V compatible ISA

Product name
Flip8051-Cyclone Flip80251-Typhoon Flip80251-Hurricane RISC-V-Tornado
Cache controller, Timers, PCA, I2C, SPI, UART, I/O Ports, Interrupt controller...
µvision™ & CA51 SmartVision™ & SmartCC80251 or CA251 SmartVision™ & GCC
BIRD™ with 4-wire JTAG interface BIRD Owl™ with 4-wire JTAG or 2-wire TWIG interfaces BIRD-V™ with 4-wire JTAG
Typical application requirements
Low activity with ultra-low leakage High volume with mid-range performance and low power

R-Stratus-LP is the first cache controller silicon IP optimized to address low-power challenges. It indeed relies on an innovative architecture which drastically reduces the number of flash accesses, by up to 1,000 times, whatever the targeted CPU frequency. It also enable on-the-fly reconfiguration of relevant cache parameters for specific application program characteristics so as to achieve ultimate power savings.

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Latest News : R-Stratus-LP silicon IP reduces significantly power consumption of flash memories…


Dolphin Integration powers its offering of microcontroller cores with a complete offering for software development and debug.

For 80251 cores, SmartVision™ comes as an upgrade to μVision™ IDE from Keil as it adds the means to model the complete microcontroller sub-system and not only the core processor with its traditional peripherals.

BIRD provides a Build-In Real-time Debug solution for a fast and efficient embedded programming and debugging for the 8051, 80251 and RISC-V Tornado microcontroller cores at the minimal cost. Its innovative features for detecting bugs represent a step forward in terms of quality and flexibility with respect to existing solutions.

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Memory sub-system area minimization

Reducing the silicon area of microcontroller sub-system requires minimizing the area of the microcontroller core plus its program memory (located in RAM or Flash).

The 80251/80351 instruction set architectures reduce the program memory area by improving code density. When associated with our Flip 80251/80351 implementations, the microcontroller cores area themselves are optimized.

Area of microcontroller cores with associated program memory

Low power optimization

The power consumption of the microcontroller sub-system is optimized thanks to:

  • denser code reducing the number of memory access,
  • faster execution of instructions enabling the microcontroller core to be more often in power saving modes,
  • low power implementation with clock gating and enable signals on combinatory logic.

Power consumption of Dolphin Integration’s microcontroller cores versus processing power*

Application specific requirements

Microcontroller cores from Dolphin Integration offer a co-processor interface.

This interface favors the association of a dedicated co-processor with the microcontroller core to meet application specific requirements. Such an approach avoids using more complex general purpose microcontroller cores which will consume more and waste silicon area.

Key benefits of using co-processors:

  • optimized and application-oriented instruction set : audio, cryptography, touchscreen...
  • specific data width to match data types used in application software
  • specifically addressable memory space
  • smart distribution of tasks enabling management of power modes
  • faster execution of the application software

*MAC: Multiplier and Accumulator / ALU: Arithmetic Logic Unit / ASU: Addressing and Sequencing Unit

Vendors’ datasheet often detail the performances of microcontroller cores with different units and in different technology nodes and processes. It is thus impossible for users to compare «apples with apples» and select the microcontroller core which best suits their need by only comparing datasheets.

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Efficient microcontroller core assessment

Discover THE unique solution to build the embedded control network of a low power SoC with Maestro™

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