Low power design flow

Key benefits of Dolphin offering for Low-Power Design

  • Dedicated Silicon IPs for the PMNet Architecture:
    • Upstream and Downstream regulators: iLR, nLR, qLR, eSR
    • CLICK - Composite Logic Islet Construction Kit – enabling the highest density, includes
      • level shifters
      • power switches
      • Transition Ramp Cell – TRC
  • Know-How in simulation and use of dedicated view EPLAM (Electrical Performance Logic and Analog Model) for specific verifications :
    • Noise Propagation Checks – NPC
    • Mode Transition Checks – MTC
  • Early floorplan for defining the SoC islets and enabling the parallelization of the next design stages for the islets and the top design:
    • a preliminary power regulator sizing
    • an early assessment or the IR-Drop and power management network budgets
  • Regular Power Regulator Sizing
    • At relevant stages (refer to the integration flow page 2)
    • Compromise between Power Optimization and functionality
  • Use of scripts for an automatic ring construction: power switches automatic placement and interconnection
    • Secure implementation
    • Optimization of the number of power switches

1. Synoptics

  • Modeling to assess the performance of your ASIC/SoC with its application schematics
  • Preliminary floorplan: islet outlines, Power Management Network (PMNet) definition, power intent and preliminary generation of UPF/CPF files
  • Budgeting for IR-Drop, Power Regulator Sizing, Timing, Area, SNR, jitter etc.
  • IP procurement and technology choice
  • Usage of specific models, EPLAM (Electrical Performance Logic and Analog Model) for various verifications (functional, noise – Noise Propagation Checks – NPC: Power – MTC: Mode Transmission Checks etc.)

2. Floorplan

  • Power pad placement
  • Building top level power grid & power ring for power islets
  • MTC check with EPLAM adjusted [2⇒1]
  • Regulators positioning and interconnecting

3. Hierarchical RTL Design

  • Power-aware hierarchy
  • Transition ramp cell instantiation
  • Clock network definition
  • Activity Control Unit / Regulator Control Unit design

4. Macro-block/Islet Synthesis

  • Hierarchical synthesis and testability approach per islet through hard block integration
  • Timing constraint budgeting
  • Turning hard macros into power islets, if presenting an advantage for the SoC

5. Macro-block/Islet Clock Tree Synthesis, Power Regulator Sizing & Layout

  • High-Frequency IR-Drop analysis (Clock edge transition management)
  • MTC checks with EPLAM adjusted with power consumption analysis for voltage regulator adjustment [5⇒2]
  • Power Regulator Sizing [5⇒2]
  • Replacement script of clock tree buffers for pulsed latch
  • Critical review for the clock tree [5⇒4]
  • Islet merging with downstream regulator

6. Top RTL & Synthesis

  • Sea of Gates fill-in synthesis and testability insertion at top level
  • Reassessment of budgets between macro-blocks/islets at top level

7. Top CTS, PRS & Layout

  • IP merge to protect the Intellectual Property
  • Final clock network optimization [7⇒6]
  • Final power management network optimization
  • High Frequency IR-Drop analysis
  • Insertion of upstream regulators
  • MTC check as added signoff verification [7⇒6]

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