SoC design & ASIC services

The single challenge of SoC integrator is to tape-out a circuit right-on-first pass, but experience shows that a significant part of integration failures result from lack of work on specifications. Dolphin Integration proposes its complete expertise to answer to the customer through its custom fabless service line: HARMONIE.

The key points are first to introduce a rigorous specification writing process, then to perform a hierarchical SoC Integration to guarantee the specifications.

As a result, HARMONIE exploits the hard-level of Dolphin’s Virtual Components (ViC) or other IP providers with rigorous schemes for guiding the optimization of power regulation and noise resilience. To help these optimizations, HARMONIE takes all the benefits of its virtual platform based on Dolphin’s Missing EDA Links. This virtual platform offers an add-on to the existing development platforms.

SoC design & ASIC services

Hierarchical SoC Architecture IP Procurement RTL Design Synthesis Floorplan Clock Tree Synthesis Routing Layout GDSII

click on yellow buttons to see each step

Hierarchical SoC Architecture

  • Power Management Network Specification: full hierarchy of regulators for supplying each islet with the power needed for reaching performances based on know-how of implementation of power optimized blocks within a SoC
  • Partitioning and DfT
  • RTL coding rules and analog schematic
  • Silicon IP integration
  • Mixed-Signal simulation and virtual test

IP procurement

  • Capability of building objective specifications of required silicon IPs
  • IP providers selection through rigorous criteria comparison matrix:
  • Technical criteria
  • Cost criteria
  • Guaranty criteria (risks, lead time, success stories etc.)
  • Full procedure for validation of deliverables
  • Valuable partnerships for easiest negotiations

RTL Design

  • Repartition in power islet: Construction of islets and choice of their regulators dedicated to each islet performances through rigorous guideline procedures
  • Use of Transition Ramp Cells for control of power switch for extinction and retention islets
  • Electrical Performances of Logical and Analog Models – EPLAM - simulation for PMNet specifications


  • Library selection: from Dolphin Integration – Sesame or from other IP supplier
  • Use of scripts on data path, placement, clock tree, routing, for higher density or for high speed or for low power consumption
  • CLICK - Composite Logic Islet Construction Kit, tool box enabling the construction and integration of both voltage and power islets, allowing a drastic reduction of power
  • EPLAM Simulation for PMNet adjustment


  • Final Floorplan with power supply path optimization for IR Drop limitation: placement and power grid sizing rules
  • PMNet placement and powerpad placement
  • I/O pads placement
  • Hard macro placement
  • IR Drop verification

Clock Tree Synthesis

  • Critical path synthesis
  • Clock path optimization
  • Deskewing technics to improve the overall speed


  • Timing driven routing
  • Routing guidelines for power supply and clock path in order to respect power and noise templates provided in Silicon IP specifications

Layout - GDSII

  • Final verifications:
  • Parasitics Extractions
  • Sign-off Timing analysis
  • DRC, LVS, ERC, checks
  • IR Drop verifications
  • EPLAM simulation with bonding information and application schematics

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