Cost-effective design of uLP SoCs at 55 nm
Our increasingly connected world contains an ever-growing number of interactive and smart devices. The adoption of efficient but complex SoC architectures satisfying the low power requirements raises new design challenges.
Dolphin Integration’s unique “Trio” at 55 nm enables the cost and time-efficient design of ultra-low power SoCs partitioned in multiple power domains.
Discover right away this silicon proven and Demochip proven consistent offering!
Targeted markets and applications
Total solution for the Always-On domain to reach the lowest power consumption.
Designed to support operation down to Near-Threshold Voltage to reach below 0.5 µA in SoC sleep modes.